2017-09-19 12:14:52 +08:00
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#ifndef __AM33XX_H__
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#define __AM33XX_H__
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#define __REG32(x) (*((volatile unsigned int *)(x)))
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#define __REG16(x) (*((volatile unsigned short *)(x)))
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/*
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* Peripheral addresses
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*/
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#define REALVIEW_UART0_BASE 0x10009000 /* UART 0 */
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#define REALVIEW_UART1_BASE 0x1000A000 /* UART 1 */
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#define REALVIEW_UART2_BASE 0x1000B000 /* UART 2 */
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#define REALVIEW_UART3_BASE 0x1000C000 /* UART 3 */
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#define REALVIEW_SSP_BASE 0x1000D000 /* Synchronous Serial Port */
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#define REALVIEW_WATCHDOG0_BASE 0x1000F000 /* Watchdog 0 */
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#define REALVIEW_WATCHDOG_BASE 0x10010000 /* watchdog interface */
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#define REALVIEW_TIMER0_1_BASE 0x10011000 /* Timer 0 and 1 */
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#define REALVIEW_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */
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#define REALVIEW_GPIO0_BASE 0x10013000 /* GPIO port 0 */
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#define REALVIEW_RTC_BASE 0x10017000 /* Real Time Clock */
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#define REALVIEW_TIMER4_5_BASE 0x10018000 /* Timer 4/5 */
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#define REALVIEW_TIMER6_7_BASE 0x10019000 /* Timer 6/7 */
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#define REALVIEW_SCTL_BASE 0x10001000 /* System Controller */
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#define REALVIEW_CLCD_BASE 0x10020000 /* CLCD */
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#define REALVIEW_ONB_SRAM_BASE 0x10060000 /* On-board SRAM */
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#define REALVIEW_DMC_BASE 0x100E0000 /* DMC configuration */
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#define REALVIEW_SMC_BASE 0x100E1000 /* SMC configuration */
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#define REALVIEW_CAN_BASE 0x100E2000 /* CAN bus */
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#define REALVIEW_GIC_CPU_BASE 0x1E000100 /* Generic interrupt controller CPU interface */
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#define REALVIEW_FLASH0_BASE 0x40000000
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#define REALVIEW_FLASH0_SIZE SZ_64M
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#define REALVIEW_FLASH1_BASE 0x44000000
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#define REALVIEW_FLASH1_SIZE SZ_64M
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#define VEXPRESS_SRAM_BASE 0x48000000
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#define REALVIEW_ETH_BASE 0x4E000000 /* Ethernet */
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2017-11-30 16:33:16 +08:00
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#define VEXPRESS_ETH_BASE 0x4E000000 /* Ethernet */
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2017-09-19 12:14:52 +08:00
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#define REALVIEW_USB_BASE 0x4F000000 /* USB */
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#define REALVIEW_GIC_DIST_BASE 0x1E001000 /* Generic interrupt controller distributor */
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#define REALVIEW_LT_BASE 0xC0000000 /* Logic Tile expansion */
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#define REALVIEW_SDRAM6_BASE 0x70000000 /* SDRAM bank 6 256MB */
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#define REALVIEW_SDRAM7_BASE 0x80000000 /* SDRAM bank 7 256MB */
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#define REALVIEW_SYS_PLD_CTRL1 0x74
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/*
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* PCI regions
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*/
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#define REALVIEW_PCI_BASE 0x90040000 /* PCI-X Unit base */
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#define REALVIEW_PCI_IO_BASE 0x90050000 /* IO Region on AHB */
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#define REALVIEW_PCI_MEM_BASE 0xA0000000 /* MEM Region on AHB */
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#define REALVIEW_PCI_BASE_SIZE 0x10000 /* 16 Kb */
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#define REALVIEW_PCI_IO_SIZE 0x1000 /* 4 Kb */
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#define REALVIEW_PCI_MEM_SIZE 0x20000000 /* 512 MB */
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/*
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* Memory definitions
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*/
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#define REALVIEW_BOOT_ROM_LO 0x30000000 /* DoC Base (64Mb)... */
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#define REALVIEW_BOOT_ROM_HI 0x30000000
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#define REALVIEW_BOOT_ROM_BASE REALVIEW_BOOT_ROM_HI /* Normal position */
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#define REALVIEW_BOOT_ROM_SIZE SZ_64M
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#define REALVIEW_SSRAM_BASE /* REALVIEW_SSMC_BASE ? */
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#define REALVIEW_SSRAM_SIZE SZ_2M
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/*
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* SDRAM
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*/
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#define REALVIEW_SDRAM_BASE 0x00000000
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/*
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* Logic expansion modules
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*
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*/
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#define IRQ_PBA8_GIC_START 32
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/*
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* PB-A8 on-board gic irq sources
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*/
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#define IRQ_PBA8_WATCHDOG (IRQ_PBA8_GIC_START + 0) /* Watchdog timer */
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#define IRQ_PBA8_SOFT (IRQ_PBA8_GIC_START + 1) /* Software interrupt */
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#define IRQ_PBA8_TIMER0_1 (IRQ_PBA8_GIC_START + 2) /* Timer 0/1 (default timer) */
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#define IRQ_PBA8_TIMER2_3 (IRQ_PBA8_GIC_START + 3) /* Timer 2/3 */
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#define IRQ_PBA8_RTC (IRQ_PBA8_GIC_START + 4) /* Timer 2/3 */
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2017-11-30 16:33:16 +08:00
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#define IRQ_VEXPRESS_A9_RTC (IRQ_PBA8_GIC_START + 4)
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2017-09-19 12:14:52 +08:00
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#define IRQ_PBA8_UART0 (IRQ_PBA8_GIC_START + 5) /* UART 0 on development chip */
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#define IRQ_PBA8_UART1 (IRQ_PBA8_GIC_START + 6) /* UART 1 on development chip */
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#define IRQ_PBA8_UART2 (IRQ_PBA8_GIC_START + 7) /* UART 2 on development chip */
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#define IRQ_PBA8_UART3 (IRQ_PBA8_GIC_START + 8) /* UART 3 on development chip */
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2017-11-30 16:33:16 +08:00
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#define IRQ_VEXPRESS_A9_KBD (IRQ_PBA8_GIC_START + 12)
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#define IRQ_VEXPRESS_A9_MOUSE (IRQ_PBA8_GIC_START + 13)
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#define IRQ_VEXPRESS_A9_CLCD (IRQ_PBA8_GIC_START + 14)
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#define IRQ_VEXPRESS_A9_ETH (IRQ_PBA8_GIC_START + 15)
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2017-09-19 12:14:52 +08:00
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/* 9 reserved */
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#define IRQ_PBA8_SSP (IRQ_PBA8_GIC_START + 11) /* Synchronous Serial Port */
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#define IRQ_PBA8_SCI (IRQ_PBA8_GIC_START + 16) /* Smart Card Interface */
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#define IRQ_PBA8_MMCI0A (IRQ_PBA8_GIC_START + 17) /* Multimedia Card 0A */
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#define IRQ_PBA8_MMCI0B (IRQ_PBA8_GIC_START + 18) /* Multimedia Card 0B */
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#define IRQ_PBA8_AACI (IRQ_PBA8_GIC_START + 19) /* Audio Codec */
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#define IRQ_PBA8_KMI0 (IRQ_PBA8_GIC_START + 20) /* Keyboard/Mouse port 0 */
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#define IRQ_PBA8_KMI1 (IRQ_PBA8_GIC_START + 21) /* Keyboard/Mouse port 1 */
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#define IRQ_PBA8_CHARLCD (IRQ_PBA8_GIC_START + 22) /* Character LCD */
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#define IRQ_PBA8_CLCD (IRQ_PBA8_GIC_START + 23) /* CLCD controller */
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#define IRQ_PBA8_DMAC (IRQ_PBA8_GIC_START + 24) /* DMA controller */
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#define IRQ_PBA8_PWRFAIL (IRQ_PBA8_GIC_START + 25) /* Power failure */
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#define IRQ_PBA8_PISMO (IRQ_PBA8_GIC_START + 26) /* PISMO interface */
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#define IRQ_PBA8_DoC (IRQ_PBA8_GIC_START + 27) /* Disk on Chip memory controller */
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#define IRQ_PBA8_ETH (IRQ_PBA8_GIC_START + 28) /* Ethernet controller */
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#define IRQ_PBA8_USB (IRQ_PBA8_GIC_START + 29) /* USB controller */
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#define IRQ_PBA8_TSPEN (IRQ_PBA8_GIC_START + 30) /* Touchscreen pen */
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#define IRQ_PBA8_TSKPAD (IRQ_PBA8_GIC_START + 31) /* Touchscreen keypad */
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#define IRQ_PBA8_PMU (IRQ_PBA8_GIC_START + 47) /* Cortex-A8 PMU */
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/* ... */
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#define IRQ_PBA8_PCI0 (IRQ_PBA8_GIC_START + 50)
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#define IRQ_PBA8_PCI1 (IRQ_PBA8_GIC_START + 51)
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#define IRQ_PBA8_PCI2 (IRQ_PBA8_GIC_START + 52)
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#define IRQ_PBA8_PCI3 (IRQ_PBA8_GIC_START + 53)
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#define IRQ_PBA8_SMC -1
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#define IRQ_PBA8_SCTL -1
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#define NR_GIC_PBA8 1
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/*
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* Only define NR_IRQS if less than NR_IRQS_PBA8
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*/
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#define NR_IRQS_PBA8 (IRQ_PBA8_GIC_START + 64)
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/* ------------------------------------------------------------------------
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* RealView Registers
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* ------------------------------------------------------------------------
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*
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*/
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#define REALVIEW_SYS_ID_OFFSET 0x00
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#define REALVIEW_SYS_SW_OFFSET 0x04
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#define REALVIEW_SYS_LED_OFFSET 0x08
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#define REALVIEW_SYS_OSC0_OFFSET 0x0C
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#define REALVIEW_SYS_OSC1_OFFSET 0x10
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#define REALVIEW_SYS_OSC2_OFFSET 0x14
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#define REALVIEW_SYS_OSC3_OFFSET 0x18
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#define REALVIEW_SYS_OSC4_OFFSET 0x1C /* OSC1 for RealView/AB */
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#define REALVIEW_SYS_LOCK_OFFSET 0x20
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#define REALVIEW_SYS_100HZ_OFFSET 0x24
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#define REALVIEW_SYS_CFGDATA1_OFFSET 0x28
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#define REALVIEW_SYS_CFGDATA2_OFFSET 0x2C
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#define REALVIEW_SYS_FLAGS_OFFSET 0x30
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#define REALVIEW_SYS_FLAGSSET_OFFSET 0x30
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#define REALVIEW_SYS_FLAGSCLR_OFFSET 0x34
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#define REALVIEW_SYS_NVFLAGS_OFFSET 0x38
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#define REALVIEW_SYS_NVFLAGSSET_OFFSET 0x38
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#define REALVIEW_SYS_NVFLAGSCLR_OFFSET 0x3C
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#define REALVIEW_SYS_RESETCTL_OFFSET 0x40
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#define REALVIEW_SYS_PCICTL_OFFSET 0x44
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#define REALVIEW_SYS_MCI_OFFSET 0x48
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#define REALVIEW_SYS_FLASH_OFFSET 0x4C
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#define REALVIEW_SYS_CLCD_OFFSET 0x50
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#define REALVIEW_SYS_CLCDSER_OFFSET 0x54
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#define REALVIEW_SYS_BOOTCS_OFFSET 0x58
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#define REALVIEW_SYS_24MHz_OFFSET 0x5C
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#define REALVIEW_SYS_MISC_OFFSET 0x60
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#define REALVIEW_SYS_IOSEL_OFFSET 0x70
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#define REALVIEW_SYS_PROCID_OFFSET 0x84
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#define REALVIEW_SYS_TEST_OSC0_OFFSET 0xC0
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#define REALVIEW_SYS_TEST_OSC1_OFFSET 0xC4
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#define REALVIEW_SYS_TEST_OSC2_OFFSET 0xC8
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#define REALVIEW_SYS_TEST_OSC3_OFFSET 0xCC
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#define REALVIEW_SYS_TEST_OSC4_OFFSET 0xD0
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#define REALVIEW_SYS_BASE 0x10000000
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#define REALVIEW_SYS_ID (REALVIEW_SYS_BASE + REALVIEW_SYS_ID_OFFSET)
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#define REALVIEW_SYS_SW (REALVIEW_SYS_BASE + REALVIEW_SYS_SW_OFFSET)
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#define REALVIEW_SYS_LED (REALVIEW_SYS_BASE + REALVIEW_SYS_LED_OFFSET)
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#define REALVIEW_SYS_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC0_OFFSET)
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#define REALVIEW_SYS_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC1_OFFSET)
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#define REALVIEW_SYS_LOCK (REALVIEW_SYS_BASE + REALVIEW_SYS_LOCK_OFFSET)
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#define REALVIEW_SYS_100HZ (REALVIEW_SYS_BASE + REALVIEW_SYS_100HZ_OFFSET)
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#define REALVIEW_SYS_CFGDATA1 (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA1_OFFSET)
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#define REALVIEW_SYS_CFGDATA2 (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA2_OFFSET)
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#define REALVIEW_SYS_FLAGS (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGS_OFFSET)
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#define REALVIEW_SYS_FLAGSSET (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSSET_OFFSET)
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#define REALVIEW_SYS_FLAGSCLR (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSCLR_OFFSET)
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#define REALVIEW_SYS_NVFLAGS (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGS_OFFSET)
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#define REALVIEW_SYS_NVFLAGSSET (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSSET_OFFSET)
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#define REALVIEW_SYS_NVFLAGSCLR (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSCLR_OFFSET)
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#define REALVIEW_SYS_RESETCTL (REALVIEW_SYS_BASE + REALVIEW_SYS_RESETCTL_OFFSET)
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#define REALVIEW_SYS_PCICTL (REALVIEW_SYS_BASE + REALVIEW_SYS_PCICTL_OFFSET)
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#define REALVIEW_SYS_MCI (REALVIEW_SYS_BASE + REALVIEW_SYS_MCI_OFFSET)
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#define REALVIEW_SYS_FLASH (REALVIEW_SYS_BASE + REALVIEW_SYS_FLASH_OFFSET)
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#define REALVIEW_SYS_CLCD (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCD_OFFSET)
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#define REALVIEW_SYS_CLCDSER (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCDSER_OFFSET)
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#define REALVIEW_SYS_BOOTCS (REALVIEW_SYS_BASE + REALVIEW_SYS_BOOTCS_OFFSET)
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#define REALVIEW_SYS_24MHz (REALVIEW_SYS_BASE + REALVIEW_SYS_24MHz_OFFSET)
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#define REALVIEW_SYS_MISC (REALVIEW_SYS_BASE + REALVIEW_SYS_MISC_OFFSET)
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#define REALVIEW_SYS_IOSEL (REALVIEW_SYS_BASE + REALVIEW_SYS_IOSEL_OFFSET)
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#define REALVIEW_SYS_PROCID (REALVIEW_SYS_BASE + REALVIEW_SYS_PROCID_OFFSET)
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#define REALVIEW_SYS_TEST_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC0_OFFSET)
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#define REALVIEW_SYS_TEST_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC1_OFFSET)
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#define REALVIEW_SYS_TEST_OSC2 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC2_OFFSET)
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#define REALVIEW_SYS_TEST_OSC3 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC3_OFFSET)
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#define REALVIEW_SYS_TEST_OSC4 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC4_OFFSET)
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#define REALVIEW_SYS_CTRL_LED (1 << 0)
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/* ------------------------------------------------------------------------
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* RealView control registers
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* ------------------------------------------------------------------------
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*/
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/*
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* REALVIEW_IDFIELD
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*
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* 31:24 = manufacturer (0x41 = ARM)
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* 23:16 = architecture (0x08 = AHB system bus, ASB processor bus)
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* 15:12 = FPGA (0x3 = XVC600 or XVC600E)
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* 11:4 = build value
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* 3:0 = revision number (0x1 = rev B (AHB))
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*/
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/*
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* REALVIEW_SYS_LOCK
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* control access to SYS_OSCx, SYS_CFGDATAx, SYS_RESETCTL,
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* SYS_CLD, SYS_BOOTCS
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*/
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#define REALVIEW_SYS_LOCK_LOCKED (1 << 16)
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#define REALVIEW_SYS_LOCKVAL 0xA05F
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#define REALVIEW_SYS_LOCKVAL_MASK 0xFFFF /* write 0xA05F to enable write access */
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/*
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* REALVIEW_SYS_FLASH
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*/
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#define REALVIEW_FLASHPROG_FLVPPEN (1 << 0) /* Enable writing to flash */
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/*
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* REALVIEW_INTREG
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* - used to acknowledge and control MMCI and UART interrupts
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*/
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#define REALVIEW_INTREG_WPROT 0x00 /* MMC protection status (no interrupt generated) */
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#define REALVIEW_INTREG_RI0 0x01 /* Ring indicator UART0 is asserted, */
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#define REALVIEW_INTREG_CARDIN 0x08 /* MMCI card in detect */
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/* write 1 to acknowledge and clear */
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#define REALVIEW_INTREG_RI1 0x02 /* Ring indicator UART1 is asserted, */
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#define REALVIEW_INTREG_CARDINSERT 0x03 /* Signal insertion of MMC card */
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/*
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* LED settings, bits [7:0]
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*/
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#define REALVIEW_SYS_LED0 (1 << 0)
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#define REALVIEW_SYS_LED1 (1 << 1)
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#define REALVIEW_SYS_LED2 (1 << 2)
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#define REALVIEW_SYS_LED3 (1 << 3)
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#define REALVIEW_SYS_LED4 (1 << 4)
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#define REALVIEW_SYS_LED5 (1 << 5)
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#define REALVIEW_SYS_LED6 (1 << 6)
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#define REALVIEW_SYS_LED7 (1 << 7)
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#define ALL_LEDS 0xFF
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#define LED_BANK REALVIEW_SYS_LED
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/*
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* Control registers
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*/
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#define REALVIEW_IDFIELD_OFFSET 0x0 /* RealView build information */
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#define REALVIEW_FLASHPROG_OFFSET 0x4 /* Flash devices */
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#define REALVIEW_INTREG_OFFSET 0x8 /* Interrupt control */
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#define REALVIEW_DECODE_OFFSET 0xC /* Fitted logic modules */
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/*
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* Clean base - dummy
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*
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*/
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#define CLEAN_BASE REALVIEW_BOOT_ROM_HI
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/*
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* System controller bit assignment
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*/
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#define REALVIEW_REFCLK 0
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#define REALVIEW_TIMCLK 1
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#define REALVIEW_TIMER1_EnSel 15
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#define REALVIEW_TIMER2_EnSel 17
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#define REALVIEW_TIMER3_EnSel 19
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#define REALVIEW_TIMER4_EnSel 21
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struct rt_hw_register
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{
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unsigned long r0;
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unsigned long r1;
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unsigned long r2;
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unsigned long r3;
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unsigned long r4;
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unsigned long r5;
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unsigned long r6;
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unsigned long r7;
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unsigned long r8;
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unsigned long r9;
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unsigned long r10;
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unsigned long fp;
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unsigned long ip;
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unsigned long sp;
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unsigned long lr;
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unsigned long pc;
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unsigned long cpsr;
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unsigned long ORIG_r0;
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};
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#include <armv7.h>
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/* Interrupt Control Interface */
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#define ARM_GIC_CPU_BASE 0x1E000000
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/* number of interrupts on board */
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#define ARM_GIC_NR_IRQS 96
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/* only one GIC available */
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#define ARM_GIC_MAX_NR 1
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#endif
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