2016-04-18 13:52:39 +08:00
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/*
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* This file is part of FH8620 BSP for RT-Thread distribution.
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*
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* Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
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* All rights reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Visit http://www.fullhan.com to get contact with Fullhan.
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*
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* Change Logs:
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* Date Author Notes
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*/
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#ifndef FH_MMC_H_
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#define FH_MMC_H_
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#include "fh_def.h"
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#define OFFSET_SDC_CTRL (0x0000)
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#define OFFSET_SDC_PWREN (0x0004)
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#define OFFSET_SDC_CLKDIV (0x0008)
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#define OFFSET_SDC_CLKSRC (0x000C)
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#define OFFSET_SDC_CLKENA (0x0010)
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#define OFFSET_SDC_TMOUT (0x0014)
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#define OFFSET_SDC_CTYPE (0x0018)
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#define OFFSET_SDC_BLKSIZ (0x001C)
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#define OFFSET_SDC_BYTCNT (0x0020)
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#define OFFSET_SDC_INTMASK (0x0024)
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#define OFFSET_SDC_CMDARG (0x0028)
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#define OFFSET_SDC_CMD (0x002C)
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#define OFFSET_SDC_RESP0 (0x0030)
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#define OFFSET_SDC_RESP1 (0x0034)
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#define OFFSET_SDC_RESP2 (0x0038)
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#define OFFSET_SDC_RESP3 (0x003C)
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#define OFFSET_SDC_MINTSTS (0x0040)
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#define OFFSET_SDC_RINTSTS (0x0044)
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#define OFFSET_SDC_STATUS (0x0048)
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#define OFFSET_SDC_FIFOTH (0x004C)
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#define OFFSET_SDC_CDETECT (0x0050)
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#define OFFSET_SDC_WRTPRT (0x0054)
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#define OFFSET_SDC_GPIO (0x0058)
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#define OFFSET_SDC_TCBCNT (0x005C)
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#define OFFSET_SDC_TBBCNT (0x0060)
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#define OFFSET_SDC_DEBNCE (0x0064)
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#define OFFSET_SDC_USRID (0x0068)
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#define OFFSET_SDC_VERID (0x006C)
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#define OFFSET_SDC_HCON (0x0070)
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#define OFFSET_SDC_UHS_REG (0x0074)
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#define OFFSET_SDC_RST_N (0x0078)
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#define OFFSET_SDC_BMOD (0x0080)
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#define OFFSET_SDC_PLDMND (0x0084)
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#define OFFSET_SDC_DBADDR (0x0088)
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#define OFFSET_SDC_IDSTS (0x008C)
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#define OFFSET_SDC_IDINTEN (0x0090)
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#define OFFSET_SDC_DSCADDR (0x0094)
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#define OFFSET_SDC_BUFADDR (0x0098)
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#define OFFSET_SDC_CARDTHRCTL (0x0100)
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#define OFFSET_SDC_BACK_END_POWER (0x0104)
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#define OFFSET_SDC_FIFO (0x0200)
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#define MMC_FIFO_DEPTH (16)
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#define MMC_CMD_FLAG_RESPONSE_EXPECTED BIT(6)
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#define MMC_CMD_FLAG_LONG_RESPONSE BIT(7)
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#define MMC_CMD_FLAG_CHECK_RESP_CRC BIT(8)
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#define MMC_CMD_FLAG_DATA_EXPECTED BIT(9)
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#define MMC_CMD_FLAG_WRITE_TO_CARD BIT(10)
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#define MMC_CMD_FLAG_DATA_STREAM BIT(11)
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#define MMC_CMD_FLAG_AUTO_STOP BIT(12)
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#define MMC_CMD_FLAG_WAIT_PREV_DATA BIT(13)
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#define MMC_CMD_FLAG_STOP_TRANSFER BIT(14)
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#define MMC_CMD_FLAG_SEND_INIT BIT(15)
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#define MMC_CMD_FLAG_SWITCH_VOLTAGE BIT(28)
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#define MMC_STATUS_DATA_BUSY BIT(9)
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#define MMC_CTRL_CONTROLLER_RESET BIT(0)
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#define MMC_CTRL_FIFO_RESET BIT(1)
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#define MMC_CTRL_DMA_RESET BIT(2)
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#define MMC_CTRL_INT_ENABLE BIT(4)
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#define MMC_CTRL_USE_DMA BIT(25)
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#define MMC_CMD_START_CMD BIT(31)
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#define MMC_BMOD_RESET BIT(0)
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#define MMC_CLOCK_IN (50000000)
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#define MMC_CARD_WIDTH_1BIT (0)
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#define MMC_CARD_WIDTH_4BIT (1)
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#define MMC_INT_STATUS_CARD_DETECT BIT(0)
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#define MMC_INT_STATUS_RESPONSE_ERROR BIT(1)
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#define MMC_INT_STATUS_CMD_DONE BIT(2)
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#define MMC_INT_STATUS_TRANSFER_OVER BIT(3)
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#define MMC_INT_STATUS_TX_REQUEST BIT(4)
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#define MMC_INT_STATUS_RX_REQUEST BIT(5)
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#define MMC_INT_STATUS_RESP_CRC_ERROR BIT(6)
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#define MMC_INT_STATUS_DATA_CRC_ERROR BIT(7)
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#define MMC_INT_STATUS_RESPONSE_TIMEOUT BIT(8)
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#define MMC_INT_STATUS_READ_TIMEOUT BIT(9)
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#define MMC_INT_STATUS_STARVATION_TIMEOUT BIT(10)
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#define MMC_INT_STATUS_OVERRUN_UNDERRUN BIT(11)
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#define MMC_INT_STATUS_HARDWARE_LOCKED BIT(12)
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#define MMC_INT_STATUS_START_BIT_ERROR BIT(13)
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#define MMC_INT_STATUS_AUTO_CMD_DONE BIT(14)
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#define MMC_INT_STATUS_END_BIT_ERROR BIT(15)
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#define MMC_INT_STATUS_SDIO BIT(16)
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#define MMC_INT_STATUS_ALL (~0)
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#define MMC_INIT_STATUS_DATA_ERROR (MMC_INT_STATUS_DATA_CRC_ERROR \
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| MMC_INT_STATUS_START_BIT_ERROR | MMC_INT_STATUS_END_BIT_ERROR)
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#define MMC_USE_DMA
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#ifdef MMC_USE_DMA
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#define MMC_INT_STATUS_DATA (MMC_INT_STATUS_TRANSFER_OVER | MMC_INIT_STATUS_DATA_ERROR)
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#else
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#define MMC_INT_STATUS_DATA (MMC_INT_STATUS_TRANSFER_OVER | MMC_INIT_STATUS_DATA_ERROR \
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| MMC_INT_STATUS_TX_REQUEST | MMC_INT_STATUS_RX_REQUEST)
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#endif
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#define MMC_DMA_DESC_BUFF_SIZE (0x1f00)
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typedef union
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{
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struct
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{
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UINT32 reserved :1; //0~15
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UINT32 disable_interrupt_on_completion :1; //16~31
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UINT32 last_descriptor :1; //0~15
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UINT32 first_descriptor :1; //16~31
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UINT32 sencond_address_chained :1; //0~15
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UINT32 end_of_ring :1; //16~31
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UINT32 reserved_29_6 :24; //0~15
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UINT32 card_error_summary :1; //16~31
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UINT32 own :1; //16~31
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}bit;
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UINT32 dw;
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}MMC_DMA_Descriptor0;
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typedef union
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{
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struct
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{
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UINT32 buffer1_size :13; //0~15
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UINT32 buffer2_size :13; //16~31
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UINT32 reserved_26_31 :6; //0~15
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}bit;
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UINT32 dw;
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}MMC_DMA_Descriptor1;
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typedef union
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{
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struct
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{
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UINT32 buffer_addr0 :32; //0~15
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}bit;
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UINT32 dw;
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}MMC_DMA_Descriptor2;
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typedef union
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{
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struct
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{
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UINT32 buffer_addr1 :32; //0~15
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}bit;
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UINT32 dw;
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}MMC_DMA_Descriptor3;
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typedef struct
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{
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MMC_DMA_Descriptor0 desc0; /* control and status information of descriptor */
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MMC_DMA_Descriptor1 desc1; /* buffer sizes */
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MMC_DMA_Descriptor2 desc2; /* physical address of the buffer 1 */
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MMC_DMA_Descriptor3 desc3; /* physical address of the buffer 2 */
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}MMC_DMA_Descriptors;
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struct fh_mmc_obj
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{
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rt_uint32_t id;
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rt_uint32_t irq;
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rt_uint32_t base;
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rt_uint32_t power_pin_gpio;
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MMC_DMA_Descriptors *descriptors;
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void (*mmc_reset)(struct fh_mmc_obj *);
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};
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2017-12-25 15:52:17 +08:00
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rt_inline rt_uint32_t MMC_GetCardStatus(struct fh_mmc_obj *mmc_obj)
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{
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rt_uint32_t card_status = GET_REG(mmc_obj->base + OFFSET_SDC_CDETECT);
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return card_status & 0x1;
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}
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rt_inline void MMC_StartDma(struct fh_mmc_obj *mmc_obj)
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{
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rt_uint32_t reg;
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SET_REG(mmc_obj->base + OFFSET_SDC_DBADDR, (rt_uint32_t)mmc_obj->descriptors);
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reg = GET_REG(mmc_obj->base + OFFSET_SDC_BMOD);
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reg |= 1 << 7;
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SET_REG(mmc_obj->base + OFFSET_SDC_BMOD, reg);
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}
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rt_inline void MMC_StopDma(struct fh_mmc_obj *mmc_obj)
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{
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rt_uint32_t reg;
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reg = GET_REG(mmc_obj->base + OFFSET_SDC_BMOD);
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reg &= ~(1 << 7);
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SET_REG(mmc_obj->base + OFFSET_SDC_BMOD, reg);
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}
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rt_inline rt_uint32_t MMC_GetWaterlevel(struct fh_mmc_obj *mmc_obj)
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{
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return (GET_REG(mmc_obj->base + OFFSET_SDC_STATUS) >> 17) & 0x1fff;
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}
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rt_inline rt_uint32_t MMC_GetStatus(struct fh_mmc_obj *mmc_obj)
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{
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return GET_REG(mmc_obj->base + OFFSET_SDC_STATUS);
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}
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rt_inline rt_uint32_t MMC_GetRawInterrupt(struct fh_mmc_obj *mmc_obj)
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{
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return GET_REG(mmc_obj->base + OFFSET_SDC_RINTSTS);
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}
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rt_inline rt_uint32_t MMC_GetUnmaskedInterrupt(struct fh_mmc_obj *mmc_obj)
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{
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return GET_REG(mmc_obj->base + OFFSET_SDC_MINTSTS);
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}
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rt_inline rt_uint32_t MMC_ClearRawInterrupt(struct fh_mmc_obj *mmc_obj, rt_uint32_t interrupts)
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{
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return SET_REG(mmc_obj->base + OFFSET_SDC_RINTSTS, interrupts);
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}
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rt_inline rt_uint32_t MMC_GetInterruptMask(struct fh_mmc_obj *mmc_obj)
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{
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return GET_REG(mmc_obj->base + OFFSET_SDC_INTMASK);
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}
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rt_inline rt_uint32_t MMC_SetInterruptMask(struct fh_mmc_obj *mmc_obj, rt_uint32_t mask)
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{
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return SET_REG(mmc_obj->base + OFFSET_SDC_INTMASK, mask);
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}
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rt_inline void MMC_SetByteCount(struct fh_mmc_obj *mmc_obj, rt_uint32_t bytes)
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{
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SET_REG(mmc_obj->base + OFFSET_SDC_BYTCNT, bytes);
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}
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rt_inline void MMC_SetBlockSize(struct fh_mmc_obj *mmc_obj, rt_uint32_t size)
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{
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SET_REG(mmc_obj->base + OFFSET_SDC_BLKSIZ, size);
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}
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rt_inline rt_uint32_t MMC_GetResponse(struct fh_mmc_obj *mmc_obj, int resp_num)
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{
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return GET_REG(mmc_obj->base + OFFSET_SDC_RESP0 + resp_num * 4);
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}
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rt_inline rt_uint32_t MMC_IsFifoEmpty(struct fh_mmc_obj *mmc_obj)
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{
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return (GET_REG(mmc_obj->base + OFFSET_SDC_STATUS) >> 2) & 0x1;
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}
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rt_inline rt_uint32_t MMC_IsDataStateBusy(struct fh_mmc_obj *mmc_obj)
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{
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return (GET_REG(mmc_obj->base + OFFSET_SDC_STATUS) >> 10) & 0x1;
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}
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2016-04-18 13:52:39 +08:00
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void MMC_Init(struct fh_mmc_obj *mmc_obj);
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int MMC_ResetFifo(struct fh_mmc_obj *mmc_obj);
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int MMC_SetCardWidth(struct fh_mmc_obj *mmc_obj, int width);
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int MMC_UpdateClockRegister(struct fh_mmc_obj *mmc_obj, int div);
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int MMC_SendCommand(struct fh_mmc_obj *mmc_obj, rt_uint32_t cmd, rt_uint32_t arg, rt_uint32_t flags);
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int MMC_WriteData(struct fh_mmc_obj *mmc_obj, rt_uint32_t *buf, rt_uint32_t size);
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int MMC_ReadData(struct fh_mmc_obj *mmc_obj, rt_uint32_t *buf, rt_uint32_t size);
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inline void MMC_StartDma(struct fh_mmc_obj *mmc_obj);
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inline void MMC_StopDma(struct fh_mmc_obj *mmc_obj);
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void MMC_InitDescriptors(struct fh_mmc_obj *mmc_obj, rt_uint32_t *buf, rt_uint32_t size);
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#endif /* FH_MMC_H_ */
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