408 lines
13 KiB
C
408 lines
13 KiB
C
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//*****************************************************************************
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//
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// am_hal_interrupt.c
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//! @file
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//!
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//! @brief Helper functions supporting interrupts and NVIC operation.
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//!
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//! These functions may be used for NVIC-level interrupt configuration.
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//!
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//! @addtogroup interrupt2 Interrupt (ARM NVIC support functions)
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//! @ingroup apollo2hal
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//! @{
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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// Copyright (c) 2017, Ambiq Micro
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from this
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// software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
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//
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//*****************************************************************************
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#include <stdint.h>
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#include <stdbool.h>
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#include "am_mcu_apollo.h"
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//*****************************************************************************
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//
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//! @brief Enable an interrupt.
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//!
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//! @param ui32Interrupt The ISR number of the interrupt to be enabled.
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//!
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//! This function enables an interrupt signal to the NVIC based on the provided
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//! ISR number.
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//!
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//! @return None
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//
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//*****************************************************************************
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void
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am_hal_interrupt_enable(uint32_t ui32Interrupt)
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{
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//
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// Check to see what type of interrupt this is.
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//
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if ( ui32Interrupt > 15 )
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{
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//
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// If this ISR number corresponds to a "normal" peripheral interrupt,
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// enable it using the NVIC register.
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//
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AM_REG(NVIC, ISER0) = 0x1 << ((ui32Interrupt - 16) & 0x1F);
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}
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else
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{
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//
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// If this is an ARM internal interrupt number, route it to the
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// appropriate enable register.
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//
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switch(ui32Interrupt)
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{
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case AM_HAL_INTERRUPT_BUSFAULT:
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AM_BFW(SYSCTRL, SHCSR, BUSFAULTENA, 1);
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break;
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case AM_HAL_INTERRUPT_USAGEFAULT:
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AM_BFW(SYSCTRL, SHCSR, USAGEFAULTENA, 1);
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break;
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case AM_HAL_INTERRUPT_MPUFAULT:
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AM_BFW(SYSCTRL, SHCSR, MEMFAULTENA, 1);
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break;
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}
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}
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}
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//*****************************************************************************
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//
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//! @brief Disable an interrupt.
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//!
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//! @param ui32Interrupt The ISR number of the interrupt to be disabled.
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//!
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//! This function disables an interrupt signal to the NVIC based on the
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//! provided ISR number.
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//!
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//! @return None
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//
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//*****************************************************************************
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void
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am_hal_interrupt_disable(uint32_t ui32Interrupt)
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{
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//
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// Check to see what type of interrupt this is.
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//
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if ( ui32Interrupt > 15 )
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{
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//
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// If this ISR number corresponds to a "normal" peripheral interrupt,
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// disable it using the NVIC register.
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//
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AM_REG(NVIC, ICER0) = 0x1 << ((ui32Interrupt - 16) & 0x1F);
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}
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else
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{
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//
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// If this is an ARM internal interrupt number, route it to the
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// appropriate enable register.
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//
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switch(ui32Interrupt)
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{
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case AM_HAL_INTERRUPT_BUSFAULT:
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AM_BFW(SYSCTRL, SHCSR, BUSFAULTENA, 0);
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break;
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case AM_HAL_INTERRUPT_USAGEFAULT:
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AM_BFW(SYSCTRL, SHCSR, USAGEFAULTENA, 0);
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break;
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case AM_HAL_INTERRUPT_MPUFAULT:
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AM_BFW(SYSCTRL, SHCSR, MEMFAULTENA, 0);
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break;
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}
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}
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}
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//*****************************************************************************
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//
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//! @brief Set the priority of an interrupt vector.
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//!
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//! @param ui32Interrupt is the ISR number of the interrupt to change.
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//! @param ui32Priority is the new ISR priority value.
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//!
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//! This function changes the priority value in the NVIC for the given
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//! interrupt vector number.
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//!
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//! @return None
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//
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//*****************************************************************************
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void
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am_hal_interrupt_priority_set(uint32_t ui32Interrupt, uint32_t ui32Priority)
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{
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volatile uint32_t *pui32PriorityReg;
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volatile uint32_t ui32OldPriority;
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uint32_t ui32Shift;
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//
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// Find the correct priority register.
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//
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pui32PriorityReg = (volatile uint32_t *) AM_REG_NVIC_IPR0_O;
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pui32PriorityReg += ((ui32Interrupt - 16) >> 2);
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//
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// Find the correct shift value.
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//
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ui32Shift = (((ui32Interrupt - 16) & 0x3) * 8);
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//
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// Mask out the old priority.
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//
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ui32OldPriority = *pui32PriorityReg;
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ui32OldPriority &= ~(0xFF << ui32Shift);
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//
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// OR in the new priority.
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//
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*pui32PriorityReg |= (ui32Priority << ui32Shift);
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}
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//*****************************************************************************
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//
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//! @brief Set a pending interrupt bit in the NVIC (Software Interrupt)
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//!
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//! @param ui32Interrupt is the ISR number of the interrupt to change.
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//!
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//! This function sets the specified bit in the Interrupt Set Pending (ISPR0)
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//! register. For future MCUs there may be more than one ISPR.
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//!
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//! @return None
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//
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//*****************************************************************************
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void am_hal_interrupt_pend_set(uint32_t ui32Interrupt)
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{
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//
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// Check to see if the specified interrupt is valid for this MCU
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//
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if ( ui32Interrupt > 47 )
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{
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return;
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}
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//
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// Check to see what type of interrupt this is.
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//
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if ( ui32Interrupt > 15 )
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{
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//
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// If this ISR number corresponds to a "normal" peripheral interrupt,
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// disable it using the NVIC register.
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//
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AM_REG(NVIC, ISPR0) = 0x1 << ((ui32Interrupt - 16) & 0x1F);
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}
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}
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//*****************************************************************************
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//
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//! @brief Clear a pending interrupt bit in the NVIC without servicing it
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//!
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//! @param ui32Interrupt is the ISR number of the interrupt to change.
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//!
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//! This function clears the specified bit in the Interrupt Clear Pending
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//! (ICPR0) register. For future MCUs there may be more than one ICPR. This
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//! function is useful immediately following a WFI before interrupts are
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//! re-enabled.
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//!
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//! @return None
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//
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//*****************************************************************************
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void am_hal_interrupt_pend_clear(uint32_t ui32Interrupt)
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{
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//
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// Check to see if the specified interrupt is valid for this MCU
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//
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if ( ui32Interrupt > 47 )
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{
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return;
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}
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//
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// Check to see what type of interrupt this is.
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//
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if ( ui32Interrupt > 15 )
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{
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//
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// If this ISR number corresponds to a "normal" peripheral interrupt,
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// disable it using the NVIC register.
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//
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AM_REG(NVIC, ICPR0) = 0x1 << ((ui32Interrupt - 16) & 0x1F);
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}
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}
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//*****************************************************************************
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//
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//! @brief Globally enable interrupt service routines
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//!
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//! This function allows interrupt signals from the NVIC to trigger ISR entry
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//! in the CPU. This function must be called if interrupts are to be serviced
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//! in software.
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//!
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//! @return 1 if interrupts were previously disabled, 0 otherwise.
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//
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//*****************************************************************************
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#if defined(__GNUC_STDC_INLINE__)
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uint32_t __attribute__((naked))
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am_hal_interrupt_master_enable(void)
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{
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__asm(" mrs r0, PRIMASK");
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__asm(" cpsie i");
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__asm(" bx lr");
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}
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#elif defined(__ARMCC_VERSION)
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__asm uint32_t
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am_hal_interrupt_master_enable(void)
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{
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mrs r0, PRIMASK
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cpsie i
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bx lr
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}
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#elif defined(__IAR_SYSTEMS_ICC__)
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#pragma diag_suppress = Pe940 // Suppress IAR compiler warning about missing
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// return statement on a non-void function
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__stackless uint32_t
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am_hal_interrupt_master_enable(void)
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{
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__asm(" mrs r0, PRIMASK");
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__asm(" cpsie i");
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__asm(" bx lr");
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}
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#pragma diag_default = Pe940 // Restore IAR compiler warning
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#endif
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//*****************************************************************************
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//
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//! @brief Globally disable interrupt service routines
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//!
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//! This function prevents interrupt signals from the NVIC from triggering ISR
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//! entry in the CPU. This will effectively stop incoming interrupt sources
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//! from triggering their corresponding ISRs.
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//!
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//! @note Any external interrupt signal that occurs while the master interrupt
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//! disable is active will still reach the "pending" state in the NVIC, but it
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//! will not be allowed to reach the "active" state or trigger the
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//! corresponding ISR. Instead, these interrupts are essentially "queued" until
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//! the next time the master interrupt enable instruction is executed. At that
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//! time, the interrupt handlers will be executed in order of decreasing
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//! priority.
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//!
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//! @return 1 if interrupts were previously disabled, 0 otherwise.
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//
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//*****************************************************************************
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#if defined(__GNUC_STDC_INLINE__)
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uint32_t __attribute__((naked))
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am_hal_interrupt_master_disable(void)
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{
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__asm(" mrs r0, PRIMASK");
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__asm(" cpsid i");
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__asm(" bx lr");
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}
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#elif defined(__ARMCC_VERSION)
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__asm uint32_t
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am_hal_interrupt_master_disable(void)
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{
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mrs r0, PRIMASK
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cpsid i
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bx lr
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}
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#elif defined(__IAR_SYSTEMS_ICC__)
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#pragma diag_suppress = Pe940 // Suppress IAR compiler warning about missing
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// return statement on a non-void function
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__stackless uint32_t
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am_hal_interrupt_master_disable(void)
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{
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__asm(" mrs r0, PRIMASK");
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__asm(" cpsid i");
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__asm(" bx lr");
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}
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#pragma diag_default = Pe940 // Restore IAR compiler warning
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#endif
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//*****************************************************************************
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//
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//! @brief Sets the master interrupt state based on the input.
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//!
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//! @param ui32InterruptState - Desired PRIMASK value.
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//!
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//! This function directly writes the PRIMASK register in the ARM core. A value
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//! of 1 will disable interrupts, while a value of zero will enable them.
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//!
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//! This function may be used along with am_hal_interrupt_master_disable() to
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//! implement a nesting critical section. To do this, call
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//! am_hal_interrupt_master_disable() to start the critical section, and save
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//! its return value. To complete the critical section, call
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//! am_hal_interrupt_master_set() using the saved return value as \e
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//! ui32InterruptState. This will safely restore PRIMASK to the value it
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//! contained just before the start of the critical section.
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//!
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//! @return None.
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//
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//*****************************************************************************
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#if defined(__GNUC_STDC_INLINE__)
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void __attribute__((naked))
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am_hal_interrupt_master_set(uint32_t ui32InterruptState)
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{
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__asm(" msr PRIMASK, r0");
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__asm(" bx lr");
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}
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#elif defined(__ARMCC_VERSION)
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__asm void
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am_hal_interrupt_master_set(uint32_t ui32InterruptState)
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{
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msr PRIMASK, r0
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bx lr
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}
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#elif defined(__IAR_SYSTEMS_ICC__)
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#pragma diag_suppress = Pe940 // Suppress IAR compiler warning about missing
|
||
|
|
// return statement on a non-void function
|
||
|
|
__stackless void
|
||
|
|
am_hal_interrupt_master_set(uint32_t ui32InterruptState)
|
||
|
|
{
|
||
|
|
__asm(" msr PRIMASK, r0");
|
||
|
|
__asm(" bx lr");
|
||
|
|
}
|
||
|
|
#pragma diag_default = Pe940 // Restore IAR compiler warning
|
||
|
|
#endif
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// End Doxygen group.
|
||
|
|
//! @}
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|