rtt-f030/bsp/ls1cdev/libraries/ls1c_i2c.c

/*
 * File      : ls1c_i2c.c
 * This file is part of RT-Thread RTOS
 * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 *
 * Change Logs:
 * Date           Author       Notes
 * 2017-09-06     <EFBFBD><EFBFBD>Ϊ<EFBFBD><EFBFBD>       first version
 */

// <20><>װӲ<D7B0><D3B2>i2c<32>ӿ<EFBFBD>


#include "ls1c_public.h"
#include "ls1c_regs.h"
#include "ls1c_clock.h"
#include "ls1c_i2c.h"
#include "ls1c_delay.h"



/*
 * I2C<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ի<EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><EFBFBD>ƫ<EFBFBD><EFBFBD>
 * <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݼĴ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͽ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݼĴ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƫ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͬ<EFBFBD><EFBFBD>
 * <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬<EFBFBD>Ĵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƫ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͬ<EFBFBD>ģ<EFBFBD><EFBFBD><EFBFBD>ͬ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD><EFBFBD><EFBFBD>ֻд<EFBFBD><EFBFBD>״̬<EFBFBD>Ĵ<EFBFBD><EFBFBD><EFBFBD>ֻ<EFBFBD><EFBFBD>
 */
#define LS1C_I2C_PRER_LOW_OFFSET            (0)     // <20><>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֽڼĴ<DABC><C4B4><EFBFBD>ƫ<EFBFBD><C6AB>
#define LS1C_I2C_PRER_HIGH_OFFSET           (1)     // <20><>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֽڼĴ<DABC><C4B4><EFBFBD>ƫ<EFBFBD><C6AB>
#define LS1C_I2C_CONTROL_OFFSET             (2)     // <20><><EFBFBD>ƼĴ<C6BC><C4B4><EFBFBD>ƫ<EFBFBD><C6AB>
#define LS1C_I2C_DATA_OFFSET                (3)     // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݼĴ<DDBC><C4B4><EFBFBD><EFBFBD>ͽ<EFBFBD><CDBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݼĴ<DDBC><C4B4><EFBFBD><EFBFBD><EFBFBD>ƫ<EFBFBD><C6AB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͬ<EFBFBD><CDAC>
#define LS1C_I2C_CMD_OFFSET                 (4)     // <20><><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD>ƫ<EFBFBD>ƣ<EFBFBD>ֻд
#define LS1C_I2C_STATUS_OFFSET              (4)     // ״̬<D7B4>Ĵ<EFBFBD><C4B4><EFBFBD>ƫ<EFBFBD>ƣ<EFBFBD>ֻ<EFBFBD><D6BB>


// <20><><EFBFBD>ƼĴ<C6BC><C4B4><EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD><CEBB>
#define LS1C_I2C_CONTROL_EN                 (0x80)  // i2cģ<63><C4A3>ʹ<EFBFBD><CAB9>
#define LS1C_I2C_CONTROL_IEN                (0x40)  // <20>ж<EFBFBD>ʹ<EFBFBD><CAB9>

// <20><><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD><CEBB>
#define LS1C_I2C_CMD_START                  (0x90)  // <20><><EFBFBD><EFBFBD>START<52>ź<EFBFBD>
#define LS1C_I2C_CMD_STOP                   (0x40)  // <20><><EFBFBD><EFBFBD>STOP<4F>ź<EFBFBD>
#define LS1C_I2C_CMD_READ                   (0x20)  // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>źţ<C5BA><C5A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ACK<43>ź<EFBFBD>
#define LS1C_I2C_CMD_WRITE                  (0x10)  // <20><><EFBFBD><EFBFBD>д<EFBFBD>ź<EFBFBD>
#define LS1C_I2C_CMD_READ_ACK               (0x20)  // <20><><EFBFBD><EFBFBD>ACK<43>źţ<C5BA><C5A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ź<EFBFBD><C5BA><EFBFBD>ͬ
#define LS1C_I2C_CMD_READ_NACK              (0x28)  // <20><><EFBFBD><EFBFBD>NACK<43>ź<EFBFBD>
#define LS1C_I2C_CMD_IACK                   (0x00)  // <20><><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>Ӧ<EFBFBD><D3A6><EFBFBD>ź<EFBFBD>

// ״̬<D7B4>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD><CEBB>
#define LS1C_I2C_STATUS_IF                  (0x01)  // <20>жϱ<D0B6>־λ
#define LS1C_I2C_STATUS_TIP                 (0x02)  // ָʾ<D6B8><CABE><EFBFBD><EFBFBD><EFBFBD>Ĺ<EFBFBD><C4B9>̡<EFBFBD>1<EFBFBD><31><EFBFBD><EFBFBD><EFBFBD>ڴ<EFBFBD><DAB4>䣻0<E4A3BB><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define LS1C_I2C_STATUS_ARBLOST             (0x20)  // I2C<32><43>ʧȥI2C<32><43><EFBFBD>ߵĿ<DFB5><C4BF><EFBFBD>Ȩ
#define LS1C_I2C_STATUS_BUSY                (0x40)  // I2C<32><43><EFBFBD><EFBFBD>æ<EFBFBD><C3A6>־
#define LS1C_I2C_STATUS_NACK                (0x80)  // Ӧ<><D3A6>λ<EFBFBD><CEBB>־<EFBFBD><D6BE>1<EFBFBD><31>û<EFBFBD>յ<EFBFBD>Ӧ<EFBFBD><D3A6>λ<EFBFBD><CEBB>0<EFBFBD><30><EFBFBD>յ<EFBFBD>Ӧ<EFBFBD><D3A6>λ


/*
 * <EFBFBD><EFBFBD>ȡָ<EFBFBD><EFBFBD>i2cģ<EFBFBD><EFBFBD><EFBFBD>Ļ<EFBFBD><EFBFBD><EFBFBD>ַ
 * @I2Cx I2Cģ<EFBFBD><EFBFBD><EFBFBD>ı<EFBFBD><EFBFBD><EFBFBD>
 */
void *i2c_get_base(ls1c_i2c_t I2Cx)
{
    void *base = NULL;
    
    switch (I2Cx)
    {
        case LS1C_I2C_0:
            base = (void *)LS1C_I2C0_BASE;
            break;

        case LS1C_I2C_1:
            base = (void *)LS1C_I2C1_BASE;
            break;

        case LS1C_I2C_2:
            base = (void *)LS1C_I2C2_BASE;
            break;

        default:
            base = NULL;
            break;
    }

    return base;
}


/*
 * <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD><EFBFBD><EFBFBD>д<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
 * @i2c_info_p i2cģ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ
 * @cmd <EFBFBD><EFBFBD><EFBFBD><EFBFBD>
 */
void i2c_cmd(ls1c_i2c_info_t *i2c_info_p, unsigned char cmd)
{
    void *i2c_base = i2c_get_base(i2c_info_p->I2Cx);

    reg_write_8(cmd, i2c_base + LS1C_I2C_CMD_OFFSET);

    return ;
}


/*
 * ִ<EFBFBD><EFBFBD>START<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>START<EFBFBD>ź<EFBFBD>
 * @i2c_info_p i2cģ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ
 */
void i2c_cmd_start(ls1c_i2c_info_t *i2c_info_p)
{
    i2c_cmd(i2c_info_p, LS1C_I2C_CMD_START);
    return ;
}


/*
 * ִ<EFBFBD><EFBFBD>STOP<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>STOP<EFBFBD>ź<EFBFBD>
 * @i2c_info_p i2cģ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ
 */
void i2c_cmd_stop(ls1c_i2c_info_t *i2c_info_p)
{
    i2c_cmd(i2c_info_p, LS1C_I2C_CMD_STOP);
    return ;
}


/*
 * ִ<EFBFBD><EFBFBD>д<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
 * @i2c_info_p i2cģ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ
 */
void i2c_cmd_write(ls1c_i2c_info_t *i2c_info_p)
{
    i2c_cmd(i2c_info_p, LS1C_I2C_CMD_WRITE);
    return ;
}


/*
 * ִ<EFBFBD>ж<EFBFBD>ack<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ͷ<EFBFBD>ack<EFBFBD>ź<EFBFBD>
 * @i2c_info_p i2cģ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ
 */
void i2c_cmd_read_ack(ls1c_i2c_info_t *i2c_info_p)
{
    i2c_cmd(i2c_info_p, LS1C_I2C_CMD_READ_ACK);
    return ;
}


/*
 * ִ<EFBFBD>ж<EFBFBD>nack<EFBFBD><EFBFBD><EFBFBD><EFBFBD>,<EFBFBD><EFBFBD><EFBFBD>Ͷ<EFBFBD>nack<EFBFBD>ź<EFBFBD>
 * @i2c_info_p i2cģ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ
 */
void i2c_cmd_read_nack(ls1c_i2c_info_t *i2c_info_p)
{
    i2c_cmd(i2c_info_p, LS1C_I2C_CMD_READ_NACK);
    return ;
}


/*
 * <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>Ӧ<EFBFBD><EFBFBD><EFBFBD>ź<EFBFBD>
 * @i2c_info_p i2cģ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ
 */
void i2c_cmd_iack(ls1c_i2c_info_t *i2c_info_p)
{
    i2c_cmd(i2c_info_p, LS1C_I2C_CMD_IACK);
    return ;
}


/*
 * <EFBFBD><EFBFBD>ȡ״̬<EFBFBD>Ĵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
 * @i2c_info_p i2cģ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ
 * @ret ״̬<EFBFBD>Ĵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
 */
unsigned char i2c_get_status(ls1c_i2c_info_t *i2c_info_p)
{
    void *i2c_base = i2c_get_base(i2c_info_p->I2Cx);

    return reg_read_8(i2c_base + LS1C_I2C_STATUS_OFFSET);
}


/*
 * Poll the i2c status register until the specified bit is set.
 * Returns 0 if timed out (100 msec).
 * @i2c_info_p i2cģ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ
 * @bit <EFBFBD>Ĵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ijһλ
 * @ret true or false
 */
int i2c_poll_status(ls1c_i2c_info_t *i2c_info_p, unsigned long bit)
{
    int loop_cntr = 20000;

    do {
        delay_us(1);
    } while ((i2c_get_status(i2c_info_p) & bit) && (0 < --loop_cntr));

    return (0 < loop_cntr);
}


/*
 * <EFBFBD><EFBFBD>ʼ<EFBFBD><EFBFBD>ָ<EFBFBD><EFBFBD>i2cģ<EFBFBD><EFBFBD>
 * @i2c_info_p ij<EFBFBD><EFBFBD>i2cģ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ
 */
void i2c_init(ls1c_i2c_info_t *i2c_info_p)
{
    void *i2c_base = i2c_get_base(i2c_info_p->I2Cx);
    unsigned long i2c_clock = i2c_info_p->clock;
    unsigned char ctrl = reg_read_8(i2c_base + LS1C_I2C_CONTROL_OFFSET);
    unsigned long prescale = 0;

    /* make sure the device is disabled */
    ctrl = ctrl & ~(LS1C_I2C_CONTROL_EN | LS1C_I2C_CONTROL_IEN);
    reg_write_8(ctrl, i2c_base + LS1C_I2C_CONTROL_OFFSET);

    // <20><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>
    i2c_clock = MIN(i2c_clock, LS1C_I2C_CLOCK_MAX);     // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Χ<EFBFBD><CEA7>
    prescale = clk_get_apb_rate();
    prescale = (prescale / (5 * i2c_clock)) - 1;
    reg_write_8(prescale & 0xff, i2c_base + LS1C_I2C_PRER_LOW_OFFSET);
    reg_write_8(prescale >> 8, i2c_base + LS1C_I2C_PRER_HIGH_OFFSET);
    
    // ʹ<><CAB9>
    i2c_cmd_iack(i2c_info_p);
    ctrl = ctrl | LS1C_I2C_CONTROL_EN;
    reg_write_8(ctrl, i2c_base + LS1C_I2C_CONTROL_OFFSET);

    return ;
}


/*
 * (<EFBFBD>ٷ<EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><EFBFBD><EFBFBD>ֽ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>֮<EFBFBD><EFBFBD>)<EFBFBD><EFBFBD><EFBFBD>մӻ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>͵<EFBFBD>ACK<EFBFBD>ź<EFBFBD>
 * @i2c_info_p i2cģ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ
 * @ret LS1C_I2C_ACK or LS1C_I2C_NACK
 */
ls1c_i2c_ack_t i2c_receive_ack(ls1c_i2c_info_t *i2c_info_p)
{
    ls1c_i2c_ack_t ret = LS1C_I2C_NACK;
    
    if (LS1C_I2C_STATUS_NACK & i2c_get_status(i2c_info_p))
    {
        ret = LS1C_I2C_NACK;
    }
    else
    {
        ret = LS1C_I2C_ACK;
    }

    return ret;
}


/*
 * <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
 * @i2c_info_p i2cģ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ
 * @buf <EFBFBD><EFBFBD><EFBFBD>ݻ<EFBFBD><EFBFBD><EFBFBD>
 * @len <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݵij<EFBFBD><EFBFBD><EFBFBD>
 */
ls1c_i2c_ret_t i2c_receive_data(ls1c_i2c_info_t *i2c_info_p, unsigned char *buf, int len)
{
    void *i2c_base = i2c_get_base(i2c_info_p->I2Cx);
    int i = 0;

    for (i=0; i<len; i++)
    {
        // <20><>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD>
        if (i != (len - 1))
            i2c_cmd_read_ack(i2c_info_p);
        else 
            i2c_cmd_read_nack(i2c_info_p);

        // <20>ȴ<EFBFBD><C8B4><EFBFBD>ֱ<EFBFBD><D6B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
        if (!i2c_poll_status(i2c_info_p, LS1C_I2C_STATUS_TIP))
            return LS1C_I2C_RET_TIMEOUT;

        // <20><>ȡ<EFBFBD><C8A1><EFBFBD>ݣ<EFBFBD><DDA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
        *buf++ = reg_read_8(i2c_base + LS1C_I2C_DATA_OFFSET);
    }

    return LS1C_I2C_RET_OK;
}


/*
 * <EFBFBD><EFBFBD><EFBFBD><EFBFBD>START<EFBFBD>źź͵<EFBFBD>ַ
 * @i2c_info_p i2cģ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ
 * @slave_addr <EFBFBD>ӻ<EFBFBD><EFBFBD><EFBFBD>ַ
 * @direction <EFBFBD><EFBFBD><EFBFBD>ݴ<EFBFBD><EFBFBD>䷽<EFBFBD><EFBFBD>(<EFBFBD><EFBFBD><EFBFBD><EFBFBD>д)
 */
ls1c_i2c_ret_t i2c_send_start_and_addr(ls1c_i2c_info_t *i2c_info_p, 
                                       unsigned char slave_addr,
                                       ls1c_i2c_direction_t direction)
{
    void *i2c_base = i2c_get_base(i2c_info_p->I2Cx);
    unsigned char data = 0;
    
    // <20>ȴ<EFBFBD>i2c<32><63><EFBFBD>߿<EFBFBD><DFBF><EFBFBD>
    if (!i2c_poll_status(i2c_info_p, LS1C_I2C_STATUS_BUSY))
        return LS1C_I2C_RET_TIMEOUT;

    // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD>ݼĴ<DDBC><C4B4><EFBFBD>
    data = (slave_addr << 1) | ((LS1C_I2C_DIRECTION_READ == direction) ? 1 : 0);
    reg_write_8(data , i2c_base + LS1C_I2C_DATA_OFFSET);

    // <20><>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD>
    i2c_cmd_start(i2c_info_p);

    // <20>ȴ<EFBFBD><C8B4><EFBFBD>ֱ<EFBFBD><D6B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
    if (!i2c_poll_status(i2c_info_p, LS1C_I2C_STATUS_TIP))
        return LS1C_I2C_RET_TIMEOUT;

    return LS1C_I2C_RET_OK;
}


/*
 * <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
 * @i2c_info_p i2cģ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ
 * @data <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>͵<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
 * @len <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݵij<EFBFBD><EFBFBD><EFBFBD>
 */
ls1c_i2c_ret_t i2c_send_data(ls1c_i2c_info_t *i2c_info_p, unsigned char *data, int len)
{
    void *i2c_base = i2c_get_base(i2c_info_p->I2Cx);
    int i = 0;

    for (i=0; i<len; i++)
    {
        // <20><>һ<EFBFBD><D2BB><EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD><EFBFBD><EFBFBD>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD>ݼĴ<DDBC><C4B4><EFBFBD>
        reg_write_8(*data++, i2c_base + LS1C_I2C_DATA_OFFSET);

        // <20><>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD>
        reg_write_8(LS1C_I2C_CMD_WRITE, i2c_base + LS1C_I2C_CMD_OFFSET);

        // <20>ȴ<EFBFBD><C8B4><EFBFBD>ֱ<EFBFBD><D6B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
        if (!i2c_poll_status(i2c_info_p, LS1C_I2C_STATUS_TIP))
            return LS1C_I2C_RET_TIMEOUT;

        // <20><>ȡӦ<C8A1><D3A6><EFBFBD>ź<EFBFBD>
        if (LS1C_I2C_ACK != i2c_receive_ack(i2c_info_p))
            return len;
    }

    return LS1C_I2C_RET_OK;
}



/*
 * <EFBFBD><EFBFBD><EFBFBD><EFBFBD>STOP<EFBFBD>ź<EFBFBD>
 * @i2c_info_p i2cģ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ
 */
void i2c_send_stop(ls1c_i2c_info_t *i2c_info_p)
{
    i2c_cmd_stop(i2c_info_p);
    return ;
}