2013-01-08 22:40:58 +08:00
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//*****************************************************************************
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//
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// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware.
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//
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// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
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// Software License Agreement
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//
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// Texas Instruments (TI) is supplying this software for use solely and
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// exclusively on TI's microcontroller products. The software is owned by
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// TI and/or its suppliers, and is protected under applicable copyright
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// laws. You may not combine this software with "viral" open-source
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// software in order to form a larger program.
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//
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// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
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// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
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// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
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// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
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// DAMAGES, FOR ANY REASON WHATSOEVER.
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//
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// This is part of revision 8264 of the Stellaris Firmware Development Package.
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//
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//*****************************************************************************
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#ifndef __HW_WATCHDOG_H__
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#define __HW_WATCHDOG_H__
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//*****************************************************************************
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//
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// The following are defines for the Watchdog Timer register offsets.
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//
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//*****************************************************************************
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#define WDT_O_LOAD 0x00000000 // Watchdog Load
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#define WDT_O_VALUE 0x00000004 // Watchdog Value
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#define WDT_O_CTL 0x00000008 // Watchdog Control
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#define WDT_O_ICR 0x0000000C // Watchdog Interrupt Clear
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#define WDT_O_RIS 0x00000010 // Watchdog Raw Interrupt Status
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#define WDT_O_MIS 0x00000014 // Watchdog Masked Interrupt Status
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#define WDT_O_TEST 0x00000418 // Watchdog Test
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#define WDT_O_LOCK 0x00000C00 // Watchdog Lock
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the WDT_O_LOAD register.
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//
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//*****************************************************************************
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#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value
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#define WDT_LOAD_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the WDT_O_VALUE register.
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//
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//*****************************************************************************
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#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value
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#define WDT_VALUE_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the WDT_O_CTL register.
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//
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//*****************************************************************************
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#define WDT_CTL_WRC 0x80000000 // Write Complete
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#define WDT_CTL_INTTYPE 0x00000004 // Watchdog Interrupt Type
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#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable
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#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the WDT_O_ICR register.
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//
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//*****************************************************************************
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#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear
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#define WDT_ICR_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the WDT_O_RIS register.
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//
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//*****************************************************************************
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#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the WDT_O_MIS register.
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//
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//*****************************************************************************
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#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the WDT_O_TEST register.
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//
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//*****************************************************************************
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#define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the WDT_O_LOCK register.
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//
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//*****************************************************************************
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#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock
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#define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked
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#define WDT_LOCK_LOCKED 0x00000001 // Locked
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#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the WDT_ISR, WDT_RIS, and
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// WDT_MIS registers.
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//
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//*****************************************************************************
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#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired
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//*****************************************************************************
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//
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// The following definitions are deprecated.
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//
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//*****************************************************************************
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#ifndef DEPRECATED
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//*****************************************************************************
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//
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// The following are deprecated defines for the Watchdog Timer register
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// offsets.
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//
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//*****************************************************************************
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#define WDT_O_PeriphID4 0x00000FD0
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#define WDT_O_PeriphID5 0x00000FD4
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#define WDT_O_PeriphID6 0x00000FD8
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#define WDT_O_PeriphID7 0x00000FDC
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#define WDT_O_PeriphID0 0x00000FE0
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#define WDT_O_PeriphID1 0x00000FE4
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#define WDT_O_PeriphID2 0x00000FE8
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#define WDT_O_PeriphID3 0x00000FEC
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#define WDT_O_PCellID0 0x00000FF0
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#define WDT_O_PCellID1 0x00000FF4
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#define WDT_O_PCellID2 0x00000FF8
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#define WDT_O_PCellID3 0x00000FFC
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//*****************************************************************************
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//
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// The following are deprecated defines for the bit fields in the WDT_O_TEST
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// register.
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//
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//*****************************************************************************
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#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable
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//*****************************************************************************
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//
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// The following are deprecated defines for the reset values for the WDT
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// registers.
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//
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//*****************************************************************************
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#define WDT_RV_VALUE 0xFFFFFFFF // Current value register
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#define WDT_RV_LOAD 0xFFFFFFFF // Load register
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#define WDT_RV_PCellID1 0x000000F0
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#define WDT_RV_PCellID3 0x000000B1
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#define WDT_RV_PeriphID1 0x00000018
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#define WDT_RV_PeriphID2 0x00000018
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#define WDT_RV_PCellID0 0x0000000D
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#define WDT_RV_PCellID2 0x00000005
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#define WDT_RV_PeriphID0 0x00000005
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#define WDT_RV_PeriphID3 0x00000001
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#define WDT_RV_PeriphID5 0x00000000
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#define WDT_RV_RIS 0x00000000 // Raw interrupt status register
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#define WDT_RV_CTL 0x00000000 // Control register
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#define WDT_RV_PeriphID4 0x00000000
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#define WDT_RV_PeriphID6 0x00000000
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#define WDT_RV_PeriphID7 0x00000000
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#define WDT_RV_LOCK 0x00000000 // Lock register
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#define WDT_RV_MIS 0x00000000 // Masked interrupt status register
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#endif
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#endif // __HW_WATCHDOG_H__
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