297 lines
13 KiB
C
297 lines
13 KiB
C
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#ifndef __UART_H__
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#define __UART_H__
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#define BAUD_RATE 9600
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/*
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UARTAn control register 0 (UAnCTL0)
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*/
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#define _10_UARTA_UAnCTL0_INITIALVALUE 0x10U
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/* UARTAn operation control (UAnPWR) */
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#define _00_UARTA_OPERATION_DISABLE 0x00U /* disable UARTAn operation (UARTAn reset asynchronously) */
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#define _80_UARTA_OPERATION_ENABLE 0x80U /* enable UARTAn operation */
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/* Transmission operation enable (UAnTXE) */
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#define _00_UARTA_TRANSMISSION_DISABLE 0x00U /* disable transmission operation */
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#define _40_UARTA_TRANSMISSION_ENABLE 0x40U /* enable transmission operation */
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/* Reception operation enable (UAnRXE) */
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#define _00_UARTA_RECEPTION_DISABLE 0x00U /* disable reception operation */
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#define _20_UARTA_RECEPTION_ENABLE 0x20U /* enable reception operation */
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/* Transfer direction selection (UAnDIR) */
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#define _00_UARTA_TRANSFDIR_MSB 0x00U /* MSB-first transfer */
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#define _10_UARTA_TRANSFDIR_LSB 0x10U /* LSB-first transfer */
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/* Parity selection during transmission/reception (UAnPS1,UAnPS0) */
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#define _00_UARTA_PARITY_NONE 0x00U /* no parity output/reception with no parity */
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#define _04_UARTA_PARITY_ZREO 0x04U /* 0 parity output/reception with 0 parity */
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#define _08_UARTA_PARITY_ODD 0x08U /* odd parity output/odd parity check */
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#define _0C_UARTA_PARITY_EVEN 0x0CU /* even parity output/even parity check */
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/* Specification of data character length of 1 frame of transmit/receive data (UAnCL) */
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#define _00_UARTA_DATALENGTH_7BIT 0x00U /* 7 bits */
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#define _02_UARTA_DATALENGTH_8BIT 0x02U /* 8 bits */
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/* Specification of length of stop bit for transmit data (UAnSL) */
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#define _00_UARTA_STOPLENGTH_1BIT 0x00U /* 1 bit */
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#define _01_UARTA_STOPLENGTH_2BIT 0x01U /* 2 bits */
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/*
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UARTAn base clock selects register (UAnCTL1)
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*/
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/* UAnCTL1 register (UAnCKS3 - UAnCKS0) */
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#define _00_UARTA_BASECLK_FXX_2 0x00U /* fXX/2 */
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#define _01_UARTA_BASECLK_FXX_4 0x01U /* fXX/2^2 */
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#define _02_UARTA_BASECLK_FXX_8 0x02U /* fXX/2^3 */
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#define _03_UARTA_BASECLK_FXX_16 0x03U /* fXX/2^4 */
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#define _04_UARTA_BASECLK_FXX_32 0x04U /* fXX/2^5 */
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#define _05_UARTA_BASECLK_FXX_64 0x05U /* fXX/2^6 */
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#define _06_UARTA_BASECLK_FXX_128 0x06U /* fXX/2^7 */
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#define _07_UARTA_BASECLK_FXX_256 0x07U /* fXX/2^8 */
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#define _08_UARTA_BASECLK_FXX_512 0x08U /* fXX/2^9 */
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#define _09_UARTA_BASECLK_FXX_1024 0x09U /* fXX/2^10 */
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#define _0A_UARTA_BASECLK_FXX_2048 0x0AU /* fXX/2^11 */
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#define _0B_UARTA_BASECLK_FXX_4096 0x0BU /* fXX/2^12 */
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/*
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UARTAn option control register 0 (UAnOPT0)
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*/
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#define _14_UARTA_UAnOPT0_INITIALVALUE 0x14U
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/* Transmit data level bit(UAnTDL) */
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#define _00_UARTA_TRAN_DATALEVEL_NORMAL 0x00U /* normal output of transfer data */
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#define _02_UARTA_TRAN_DATALEVEL_INVERTED 0x02U /* inverted output of transfer data */
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/* Receive data level bit(UAnRDL) */
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#define _00_UARTA_REC_DATALEVEL_NORMAL 0x00U /* normal input of transfer data */
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#define _01_UARTA_REC_DATALEVEL_INVERTED 0x01U /* inverted input of transfer data */
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/*
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CSIBn control register 0 (CBnCTL0)
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*/
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/* Specification of CSIBn operation disable/enable (CBnPWR)*/
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#define _00_CSIB_OPERATION_DISABLE 0x00U /* disable CSIBn operation and reset the CBnSTR register */
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#define _80_CSIB_OPERATION_ENABLE 0x80U /* enable CSIBn operation */
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/* Specification of transmit operation disable/enable (CBnTXE)*/
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#define _00_CSIB_TRANSMIT_DISABLE 0x00U /* disable transmit operation */
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#define _40_CSIB_TRANSMIT_ENABLE 0x40U /* enable transmit operation */
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/* Specification of receive operation disable/enable (CBnRXE)*/
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#define _00_CSIB_RECEIVE_DISABLE 0x00U /* disable receive operation */
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#define _20_CSIB_RECEIVE_ENABLE 0x20U /* enable receive operation */
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/* Specification of transfer direction mode (MSB/LSB) (CBnDIR) */
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#define _00_CSIB_DATA_MSB 0x00U /* MSB first */
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#define _10_CSIB_DATA_LSB 0x10U /* LSB first */
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/* Transfer mode specification (CBnTMS) */
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#define _00_CSIB_MODE_SINGLE 0x00U /* single transfer mode */
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#define _02_CSIB_MODE_CONTINUOUS 0x02U /* continuous transfer mode */
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/* Specification of start transfer disable/enable (CBnSCE) */
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#define _00_CSIB_STARTTRG_INVALID 0x00U /* communication start trigger invalid */
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#define _01_CSIB_STARTTRG_VALID 0x01U /* communication start trigger valid */
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/*
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CSIBn control register 1 (CBnCTL1)
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*/
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/* Specification of data transmission/reception timing in relation to SCKBn (CBnCKP, CBnDAP) */
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#define _00_CSIB_DATA_TIMING1 0x00U /* communication type 1 */
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#define _08_CSIB_DATA_TIMING2 0x08U /* communication type 2 */
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#define _10_CSIB_DATA_TIMING3 0x10U /* communication type 3 */
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#define _18_CSIB_DATA_TIMING4 0x18U /* communication type 4 */
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/* Specification of input clock (CBnCKS2 - CBnCKS0) */
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#define _00_CSIB_CLOCK_1 0x00U /* fXX /2 */
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#define _01_CSIB_CLOCK_2 0x01U /* fXX/4 */
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#define _02_CSIB_CLOCK_3 0x02U /* fXX /8 */
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#define _03_CSIB_CLOCK_4 0x03U /* fXX /16 */
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#define _04_CSIB_CLOCK_5 0x04U /* fXX /32 */
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#define _05_CSIB_CLOCK_6 0x05U /* fXX /64 */
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#define _06_CSIB_CLOCK_7 0x06U /* fBRGm */
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#define _07_CSIB_CLOCK_EXT 0x07U /* external clock SCKBn */
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/*
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CSIBn control register 2 (CBnCTL2)
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*/
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/* Serial register bit length (CBnCL3,CBnCL2,CBnCL1,CBnCL0) */
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#define _00_CSIB_DATA_LENGTH_8 0x00U /* 8 bits */
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#define _01_CSIB_DATA_LENGTH_9 0x01U /* 9 bits */
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#define _02_CSIB_DATA_LENGTH_10 0x02U /* 10 bits */
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#define _03_CSIB_DATA_LENGTH_11 0x03U /* 11 bits */
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#define _04_CSIB_DATA_LENGTH_12 0x04U /* 12 bits */
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#define _05_CSIB_DATA_LENGTH_13 0x05U /* 13 bits */
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#define _06_CSIB_DATA_LENGTH_14 0x06U /* 14 bits */
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#define _07_CSIB_DATA_LENGTH_15 0x07U /* 15 bits */
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#define _08_CSIB_DATA_LENGTH_16 0x08U /* 16 bits */
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/*
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CSIBn status register (CBnSTR)
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*/
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/* Communication status flag (CBnTSF) */
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#define _00_CSIB_COMMUNICATION_STOP 0x00U /* communication stopped */
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#define _80_CSIB_COMMUNICATING 0x80U /* communicating */
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/* Overrun error flag (CBnOVE) */
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#define _00_CSIB_OVERRUN_NONE 0x00U /* no overrun */
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#define _01_CSIB_OVERRUN 0x01U /* overrun */
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/*
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BRGm prescaler mode registers (PRSMm)
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*/
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/* Baud rate output(BGCEm) */
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#define _00_CSIB_FBRGM_DISABLE 0x00U /* baudrate output disabled */
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#define _10_CSIB_FBRGM_ENABLE 0x10U /* baudrate output enabled */
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/* Input clock selection (BGCSm1,BGCSm0) */
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#define _00_CSIB_FBGCS_0 0x00U /* fXX */
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#define _01_CSIB_FBGCS_1 0x01U /* fXX/2 */
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#define _02_CSIB_FBGCS_2 0x02U /* fXX/4 */
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#define _03_CSIB_FBGCS_3 0x03U /* fXX/8 */
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#define CB4RIC UA0RIC
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#define CB4TIC UA0TIC
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#define CB0RIC IICIC1
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/*
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IIC control register (IICCn)
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*/
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/* IIC operation enable (IICEn) */
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#define _80_IIC_OPERATION 0x80U
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#define _00_IIC_OPERATION_DISABLE 0x00U /* stop operation */
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#define _80_IIC_OPERATION_ENABLE 0x80U /* enable operation */
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/* Exit from communications (LRELn) */
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#define _40_IIC_COMMUNICATION 0x40U
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#define _00_IIC_COMMUNICATION_NORMAL 0x00U /* normal operation */
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#define _40_IIC_COMMUNICATION_EXIT 0x40U /* exit from current communication */
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/* Wait cancellation (WRELn) */
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#define _20_IIC_WAITCANCEL 0x20U
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#define _00_IIC_WAIT_NOTCANCEL 0x00U /* do not cancel wait */
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#define _20_IIC_WAIT_CANCEL 0x20U /* cancel wait */
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/* Generation of interrupt when stop condition (SPIEn) */
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#define _10_IIC_STOPINT 0x10U
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#define _00_IIC_STOPINT_DISABLE 0x00U /* disable */
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#define _10_IIC_STOPINT_ENABLE 0x10U /* enable */
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/* Wait and interrupt generation (WTIMn) */
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#define _08_IIC_WAITINT 0x08U
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#define _00_IIC_WAITINT_CLK8FALLING 0x00U /* generate at the eighth clock falling edge */
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#define _08_IIC_WAITINT_CLK9FALLING 0x08U /* generated at the ninth clock falling edge */
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/* Acknowledgement control (ACKEn) */
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#define _04_IIC_ACK 0x04
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#define _00_IIC_ACK_DISABLE 0x00U /* disable acknowledgement */
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#define _04_IIC_ACK_ENABLE 0x04U /* enable acknowledgement */
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/* Start condition trigger (STTn) */
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#define _02_IIC_STARTCONDITION 0x02U
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#define _00_IIC_START_NOTGENERATE 0x00U /* do not generate start condition */
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#define _02_IIC_START_GENERATE 0x02U /* generate start condition */
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/* Stop condition trigger (SPTn) */
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#define _01_IIC_STOPCONDITION 0x01U
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#define _00_IIC_STOP_NOTGENERATE 0x00U /* do not generate stop condition */
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#define _01_IIC_STOP_GENERATE 0x01U /* generate stop condition */
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/*
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IIC Status Register (IICSn)
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*/
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/* Master device status (MSTSn) */
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#define _80_IIC_MASTERSTATUS 0x80U
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#define _00_IIC_STATUS_NOTMASTER 0x00U /* slave device status or communication standby status */
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#define _80_IIC_STATUS_MASTER 0x80U /* master device communication status */
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/* Detection of arbitration loss (ALDn) */
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#define _40_IIC_ARBITRATION 0x40U
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#define _00_IIC_ARBITRATION_NO 0x00U /* arbitration win or no arbitration */
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#define _40_IIC_ARBITRATION_LOSS 0x40U /* arbitration loss */
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/* Detection of extension code reception (EXCn) */
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#define _20_IIC_EXTENSIONCODE 0x20U
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#define _00_IIC_EXTCODE_NOT 0x00U /* extension code not received */
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#define _20_IIC_EXTCODE_RECEIVED 0x20U /* extension code received */
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/* Detection of matching addresses (COIn) */
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#define _10_IIC_ADDRESSMATCH 0x10U
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#define _00_IIC_ADDRESS_NOTMATCH 0x00U /* addresses do not match */
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#define _10_IIC_ADDRESS_MATCH 0x10U /* addresses match */
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/* Detection of transmit/receive status (TRCn) */
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#define _08_IIC_STATUS 0x08U
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#define _00_IIC_STATUS_RECEIVE 0x00U /* receive status */
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#define _08_IIC_STATUS_TRANSMIT 0x08U /* transmit status */
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/* Detection of acknowledge signal (ACKDn) */
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#define _04_IIC_ACKDETECTION 0x04U
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#define _00_IIC_ACK_NOTDETECTED 0x00U /* ACK signal was not detected */
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#define _04_IIC_ACK_DETECTED 0x04U /* ACK signal was detected */
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/* Detection of start condition (STDn) */
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#define _02_IIC_STARTDETECTION 0x02U
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#define _00_IIC_START_NOTDETECTED 0x00U /* start condition not detected */
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#define _02_IIC_START_DETECTED 0x02U /* start condition detected */
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/* Detection of stop condition (SPDn) */
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#define _01_IIC_STOPDETECTION 0x01U
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#define _00_IIC_STOP_NOTDETECTED 0x00U /* stop condition not detected */
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#define _01_IIC_STOP_DETECTED 0x01U /* stop condition detected */
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/*
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IIC Flag Register (IICFn)
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*/
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/* STTn clear flag (STCFn) */
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#define _80_IIC_STARTFLAG 0x80U
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#define _00_IIC_STARTFLAG_GENERATE 0x00U /* generate start condition */
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#define _80_IIC_STARTFLAG_UNSUCCESSFUL 0x80U /* start condition generation unsuccessful */
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/* IIC bus status flag (IICBSYn) */
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#define _40_IIC_BUSSTATUS 0x40U
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#define _00_IIC_BUS_RELEASE 0x00U /* bus release status */
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#define _40_IIC_BUS_COMMUNICATION 0x40U /* bus communication status */
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/* Initial start enable trigger (STCENn) */
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#define _02_IIC_STARTWITHSTOP 0x02U
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#define _00_IIC_START_WITHSTOP 0x00U /* generation of a start condition upon detection of a stop condition */
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#define _02_IIC_START_WITHOUTSTOP 0x02U /* generation of a start condition without detecting a stop condition */
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/* Communication reservation function disable bit (IICRSVn) */
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#define _01_IIC_RESERVATION 0x01U
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#define _00_IIC_RESERVATION_ENABLE 0x00U /* enable communication reservation */
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#define _01_IIC_RESERVATION_DISABLE 0x01U /* disable communication reservation */
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/*
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IIC clock selection register (IICCLn)
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*/
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#define _00_IICCL_INITIALVALUE 0x00U
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/* Detection of SCL0n pin level (CLDn) */
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#define _20_IIC_SCLLEVEL 0x20U
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#define _00_IIC_SCL_LOW 0x00U /* clock line at low level */
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#define _20_IIC_SCL_HIGH 0x20U /* clock line at high level */
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/* Detection of SDA0 pin level (DADn) */
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#define _10_IIC_SDALEVEL 0x10U
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#define _00_IIC_SDA_LOW 0x00U /* data line at low level */
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#define _10_IIC_SDA_HIGH 0x10U /* data line at high level */
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/* Operation mode switching (SMCn) */
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#define _08_IIC_OPERATIONMODE 0x08U
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#define _00_IIC_MODE_STANDARD 0x00U /* operates in standard mode */
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#define _08_IIC_MODE_HIGHSPEED 0x08U /* operates in high-speed mode */
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/* Digital filter operation control (DFCn) */
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#define _04_IIC_DIGITALFILTER 0x04U
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#define _00_IIC_FILTER_OFF 0x00U /* digital filter off */
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#define _04_IIC_FILTER_ON 0x04U /* digital filter on */
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/* Operation mode switching (CLn1, CLn0) */
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#define _03_IIC_CLOCKSELECTION 0x03U
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/* Combine of (CLn1, CLn0)*/
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#define _00_IIC_CLOCK0 0x00U
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#define _01_IIC_CLOCK1 0x01U
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#define _02_IIC_CLOCK2 0x02U
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#define _03_IIC_CLOCK3 0x03U
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/*
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IIC division clock select register (OCKSn)
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*/
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#define _10_IIC_SELECTED0 0x10U
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#define _11_IIC_SELECTED1 0x11U
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#define _12_IIC_SELECTED2 0x12U
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#define _13_IIC_SELECTED3 0x13U
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#define _18_IIC_SELECTED4 0x18U
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/*
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IIC function expansion register 0 (IICXn)
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*/
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/* IIC clock expension (CLXn) */
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#define _01_IIC_CLOCKEXPENSION 0x01U
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||
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|
#define _00_IIC_EXPENSION0 0x00U
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||
|
|
#define _01_IIC_EXPENSION1 0x01U
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||
|
|
#define _80_ADDRESS_COMPLETE 0x80U
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||
|
|
#define _00_IIC_MASTER_FLAG_CLEAR 0x00U
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||
|
|
#define IICIC2 UA1RIC
|
||
|
|
#define IICIC0 UA2RIC
|
||
|
|
/*
|
||
|
|
*******************************************************************************
|
||
|
|
** Macro define
|
||
|
|
*******************************************************************************
|
||
|
|
*/
|
||
|
|
/* Selection of 8-bit counter output clock (UA1BRS7~UA1BRS0) */
|
||
|
|
#define _D0_UARTA1_BASECLK_DIVISION 0xD0U /* 4 ~ 255 */ //9600
|
||
|
|
#define _11_UARTA1_BASECLK_DIVISION 0x11U /* 4 ~ 255 */ //115200
|
||
|
|
enum TransferMode
|
||
|
|
{
|
||
|
|
SEND, RECEIVE
|
||
|
|
};
|
||
|
|
|
||
|
|
void rt_hw_uart_init(void);
|
||
|
|
|
||
|
|
#endif
|