2011-06-23 08:47:34 +08:00
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//*****************************************************************************
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//
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// udma.h - Prototypes and macros for the uDMA controller.
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//
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2011-12-23 10:59:07 +08:00
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// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved.
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2011-06-23 08:47:34 +08:00
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// Software License Agreement
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//
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// Texas Instruments (TI) is supplying this software for use solely and
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// exclusively on TI's microcontroller products. The software is owned by
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// TI and/or its suppliers, and is protected under applicable copyright
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// laws. You may not combine this software with "viral" open-source
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// software in order to form a larger program.
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//
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// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
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// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
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// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
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// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
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// DAMAGES, FOR ANY REASON WHATSOEVER.
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//
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2011-12-23 10:59:07 +08:00
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// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
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2011-06-23 08:47:34 +08:00
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//
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//*****************************************************************************
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#ifndef __UDMA_H__
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#define __UDMA_H__
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//*****************************************************************************
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//
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// If building with a C++ compiler, make all of the definitions in this header
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// have a C binding.
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//
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//*****************************************************************************
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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2011-12-23 10:59:07 +08:00
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//*****************************************************************************
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//
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//! \addtogroup udma_api
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//! @{
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//
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//*****************************************************************************
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2011-06-23 08:47:34 +08:00
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//*****************************************************************************
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//
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// A structure that defines an entry in the channel control table. These
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// fields are used by the uDMA controller and normally it is not necessary for
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// software to directly read or write fields in the table.
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//
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//*****************************************************************************
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typedef struct
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{
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//
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// The ending source address of the data transfer.
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//
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volatile void *pvSrcEndAddr;
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//
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// The ending destination address of the data transfer.
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//
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volatile void *pvDstEndAddr;
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//
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// The channel control mode.
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//
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volatile unsigned long ulControl;
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//
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// An unused location.
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//
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volatile unsigned long ulSpare;
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}
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tDMAControlTable;
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2011-12-23 10:59:07 +08:00
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//*****************************************************************************
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//
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//! A helper macro for building scatter-gather task table entries.
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//!
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//! \param ulTransferCount is the count of items to transfer for this task.
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//! \param ulItemSize is the bit size of the items to transfer for this task.
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//! \param ulSrcIncrement is the bit size increment for source data.
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//! \param pvSrcAddr is the starting address of the data to transfer.
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//! \param ulDstIncrement is the bit size increment for destination data.
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//! \param pvDstAddr is the starting address of the destination data.
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//! \param ulArbSize is the arbitration size to use for the transfer task.
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//! \param ulMode is the transfer mode for this task.
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//!
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//! This macro is intended to be used to help populate a table of uDMA tasks
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//! for a scatter-gather transfer. This macro will calculate the values for
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//! the fields of a task structure entry based on the input parameters.
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//!
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//! There are specific requirements for the values of each parameter. No
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//! checking is done so it is up to the caller to ensure that correct values
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//! are used for the parameters.
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//!
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//! The \e ulTransferCount parameter is the number of items that will be
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//! transferred by this task. It must be in the range 1-1024.
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//!
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//! The \e ulItemSize parameter is the bit size of the transfer data. It must
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//! be one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or \b UDMA_SIZE_32.
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//!
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//! The \e ulSrcIncrement parameter is the increment size for the source data.
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//! It must be one of \b UDMA_SRC_INC_8, \b UDMA_SRC_INC_16,
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//! \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE.
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//!
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//! The \e pvSrcAddr parameter is a void pointer to the beginning of the source
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//! data.
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//!
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//! The \e ulDstIncrement parameter is the increment size for the destination
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//! data. It must be one of \b UDMA_DST_INC_8, \b UDMA_DST_INC_16,
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//! \b UDMA_DST_INC_32, or \b UDMA_DST_INC_NONE.
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//!
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//! The \e pvDstAddr parameter is a void pointer to the beginning of the
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//! location where the data will be transferred.
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//!
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//! The \e ulArbSize parameter is the arbitration size for the transfer, and
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//! must be one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, and so on
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//! up to \b UDMA_ARB_1024. This is used to select the arbitration size in
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//! powers of 2, from 1 to 1024.
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//!
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//! The \e ulMode parameter is the mode to use for this transfer task. It
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//! must be one of \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO,
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//! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER. Note
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//! that normally all tasks will be one of the scatter-gather modes while the
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//! last task is a task list will be AUTO or BASIC.
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//!
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//! This macro is intended to be used to initialize individual entries of
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//! a structure of tDMAControlTable type, like this:
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//!
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//! \verbatim
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//! tDMAControlTable MyTaskList[] =
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//! {
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//! uDMATaskStructEntry(Task1Count, UDMA_SIZE_8,
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//! UDMA_SRC_INC_8, MySourceBuf,
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//! UDMA_DST_INC_8, MyDestBuf,
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//! UDMA_ARB_8, UDMA_MODE_MEM_SCATTER_GATHER),
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//! uDMATaskStructEntry(Task2Count, ... ),
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//! }
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//! \endverbatim
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//!
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//! \return Nothing; this is not a function.
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//
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//*****************************************************************************
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#define uDMATaskStructEntry(ulTransferCount, \
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ulItemSize, \
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ulSrcIncrement, \
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pvSrcAddr, \
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ulDstIncrement, \
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pvDstAddr, \
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ulArbSize, \
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ulMode) \
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{ \
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(((ulSrcIncrement) == UDMA_SRC_INC_NONE) ? (void *)(pvSrcAddr) : \
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((void *)(&((unsigned char *)(pvSrcAddr))[((ulTransferCount) << \
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((ulSrcIncrement) >> 26)) - 1]))), \
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(((ulDstIncrement) == UDMA_DST_INC_NONE) ? (void *)(pvDstAddr) : \
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((void *)(&((unsigned char *)(pvDstAddr))[((ulTransferCount) << \
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((ulDstIncrement) >> 30)) - 1]))), \
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(ulSrcIncrement) | (ulDstIncrement) | (ulItemSize) | (ulArbSize) | \
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(((ulTransferCount) - 1) << 4) | \
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((((ulMode) == UDMA_MODE_MEM_SCATTER_GATHER) || \
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((ulMode) == UDMA_MODE_PER_SCATTER_GATHER)) ? \
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(ulMode) | UDMA_MODE_ALT_SELECT : (ulMode)), 0 \
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}
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//*****************************************************************************
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//
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// Close the Doxygen group.
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//! @}
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//
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//*****************************************************************************
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2011-06-23 08:47:34 +08:00
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//*****************************************************************************
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//
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// Flags that can be passed to uDMAChannelAttributeEnable(),
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// uDMAChannelAttributeDisable(), and returned from uDMAChannelAttributeGet().
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//
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//*****************************************************************************
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#define UDMA_ATTR_USEBURST 0x00000001
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#define UDMA_ATTR_ALTSELECT 0x00000002
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#define UDMA_ATTR_HIGH_PRIORITY 0x00000004
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#define UDMA_ATTR_REQMASK 0x00000008
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#define UDMA_ATTR_ALL 0x0000000F
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//*****************************************************************************
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//
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// DMA control modes that can be passed to uDMAModeSet() and returned
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// uDMAModeGet().
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//
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//*****************************************************************************
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#define UDMA_MODE_STOP 0x00000000
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#define UDMA_MODE_BASIC 0x00000001
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#define UDMA_MODE_AUTO 0x00000002
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#define UDMA_MODE_PINGPONG 0x00000003
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#define UDMA_MODE_MEM_SCATTER_GATHER \
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0x00000004
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#define UDMA_MODE_PER_SCATTER_GATHER \
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0x00000006
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#define UDMA_MODE_ALT_SELECT 0x00000001
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//*****************************************************************************
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//
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// Channel configuration values that can be passed to uDMAControlSet().
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//
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//*****************************************************************************
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#define UDMA_DST_INC_8 0x00000000
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#define UDMA_DST_INC_16 0x40000000
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#define UDMA_DST_INC_32 0x80000000
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#define UDMA_DST_INC_NONE 0xc0000000
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#define UDMA_SRC_INC_8 0x00000000
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#define UDMA_SRC_INC_16 0x04000000
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#define UDMA_SRC_INC_32 0x08000000
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#define UDMA_SRC_INC_NONE 0x0c000000
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#define UDMA_SIZE_8 0x00000000
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#define UDMA_SIZE_16 0x11000000
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#define UDMA_SIZE_32 0x22000000
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#define UDMA_ARB_1 0x00000000
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#define UDMA_ARB_2 0x00004000
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#define UDMA_ARB_4 0x00008000
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#define UDMA_ARB_8 0x0000c000
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#define UDMA_ARB_16 0x00010000
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#define UDMA_ARB_32 0x00014000
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#define UDMA_ARB_64 0x00018000
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#define UDMA_ARB_128 0x0001c000
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#define UDMA_ARB_256 0x00020000
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#define UDMA_ARB_512 0x00024000
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#define UDMA_ARB_1024 0x00028000
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#define UDMA_NEXT_USEBURST 0x00000008
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//*****************************************************************************
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//
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// Channel numbers to be passed to API functions that require a channel number
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// ID.
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//
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//*****************************************************************************
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#define UDMA_CHANNEL_USBEP1RX 0
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#define UDMA_CHANNEL_USBEP1TX 1
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#define UDMA_CHANNEL_USBEP2RX 2
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#define UDMA_CHANNEL_USBEP2TX 3
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#define UDMA_CHANNEL_USBEP3RX 4
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#define UDMA_CHANNEL_USBEP3TX 5
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#define UDMA_CHANNEL_ETH0RX 6
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#define UDMA_CHANNEL_ETH0TX 7
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#define UDMA_CHANNEL_UART0RX 8
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#define UDMA_CHANNEL_UART0TX 9
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#define UDMA_CHANNEL_SSI0RX 10
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#define UDMA_CHANNEL_SSI0TX 11
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#define UDMA_CHANNEL_ADC0 14
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#define UDMA_CHANNEL_ADC1 15
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#define UDMA_CHANNEL_ADC2 16
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#define UDMA_CHANNEL_ADC3 17
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#define UDMA_CHANNEL_TMR0A 18
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#define UDMA_CHANNEL_TMR0B 19
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#define UDMA_CHANNEL_TMR1A 20
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#define UDMA_CHANNEL_TMR1B 21
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#define UDMA_CHANNEL_UART1RX 22
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#define UDMA_CHANNEL_UART1TX 23
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#define UDMA_CHANNEL_SSI1RX 24
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#define UDMA_CHANNEL_SSI1TX 25
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#define UDMA_CHANNEL_I2S0RX 28
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#define UDMA_CHANNEL_I2S0TX 29
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#define UDMA_CHANNEL_SW 30
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//*****************************************************************************
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//
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// Flags to be OR'd with the channel ID to indicate if the primary or alternate
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// control structure should be used.
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//
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//*****************************************************************************
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#define UDMA_PRI_SELECT 0x00000000
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#define UDMA_ALT_SELECT 0x00000020
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//*****************************************************************************
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//
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// uDMA interrupt sources, to be passed to uDMAIntRegister() and
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// uDMAIntUnregister().
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//
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//*****************************************************************************
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#define UDMA_INT_SW 62
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#define UDMA_INT_ERR 63
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//*****************************************************************************
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//
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// Channel numbers to be passed to API functions that require a channel number
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// ID. These are for secondary peripheral assignments.
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//
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//*****************************************************************************
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#define UDMA_SEC_CHANNEL_UART2RX_0 \
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0
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#define UDMA_SEC_CHANNEL_UART2TX_1 \
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1
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#define UDMA_SEC_CHANNEL_TMR3A 2
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#define UDMA_SEC_CHANNEL_TMR3B 3
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#define UDMA_SEC_CHANNEL_TMR2A_4 \
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4
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#define UDMA_SEC_CHANNEL_TMR2B_5 \
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5
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#define UDMA_SEC_CHANNEL_TMR2A_6 \
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6
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#define UDMA_SEC_CHANNEL_TMR2B_7 \
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7
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#define UDMA_SEC_CHANNEL_UART1RX \
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8
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#define UDMA_SEC_CHANNEL_UART1TX \
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9
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#define UDMA_SEC_CHANNEL_SSI1RX 10
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#define UDMA_SEC_CHANNEL_SSI1TX 11
|
|
|
|
|
#define UDMA_SEC_CHANNEL_UART2RX_12 \
|
|
|
|
|
12
|
|
|
|
|
#define UDMA_SEC_CHANNEL_UART2TX_13 \
|
|
|
|
|
13
|
|
|
|
|
#define UDMA_SEC_CHANNEL_TMR2A_14 \
|
|
|
|
|
14
|
|
|
|
|
#define UDMA_SEC_CHANNEL_TMR2B_15 \
|
|
|
|
|
15
|
|
|
|
|
#define UDMA_SEC_CHANNEL_TMR1A 18
|
|
|
|
|
#define UDMA_SEC_CHANNEL_TMR1B 19
|
|
|
|
|
#define UDMA_SEC_CHANNEL_EPI0RX 20
|
|
|
|
|
#define UDMA_SEC_CHANNEL_EPI0TX 21
|
|
|
|
|
#define UDMA_SEC_CHANNEL_ADC10 24
|
|
|
|
|
#define UDMA_SEC_CHANNEL_ADC11 25
|
|
|
|
|
#define UDMA_SEC_CHANNEL_ADC12 26
|
|
|
|
|
#define UDMA_SEC_CHANNEL_ADC13 27
|
|
|
|
|
#define UDMA_SEC_CHANNEL_SW 30
|
|
|
|
|
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
//
|
|
|
|
|
// uDMA default/secondary peripheral selections, to be passed to
|
|
|
|
|
// uDMAChannelSelectSecondary() and uDMAChannelSelectDefault().
|
|
|
|
|
//
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
#define UDMA_DEF_USBEP1RX_SEC_UART2RX \
|
|
|
|
|
0x00000001
|
|
|
|
|
#define UDMA_DEF_USBEP1TX_SEC_UART2TX \
|
|
|
|
|
0x00000002
|
|
|
|
|
#define UDMA_DEF_USBEP2RX_SEC_TMR3A \
|
|
|
|
|
0x00000004
|
|
|
|
|
#define UDMA_DEF_USBEP2TX_SEC_TMR3B \
|
|
|
|
|
0x00000008
|
|
|
|
|
#define UDMA_DEF_USBEP3RX_SEC_TMR2A \
|
|
|
|
|
0x00000010
|
|
|
|
|
#define UDMA_DEF_USBEP3TX_SEC_TMR2B \
|
|
|
|
|
0x00000020
|
|
|
|
|
#define UDMA_DEF_ETH0RX_SEC_TMR2A \
|
|
|
|
|
0x00000040
|
|
|
|
|
#define UDMA_DEF_ETH0TX_SEC_TMR2B \
|
|
|
|
|
0x00000080
|
|
|
|
|
#define UDMA_DEF_UART0RX_SEC_UART1RX \
|
|
|
|
|
0x00000100
|
|
|
|
|
#define UDMA_DEF_UART0TX_SEC_UART1TX \
|
|
|
|
|
0x00000200
|
|
|
|
|
#define UDMA_DEF_SSI0RX_SEC_SSI1RX \
|
|
|
|
|
0x00000400
|
|
|
|
|
#define UDMA_DEF_SSI0TX_SEC_SSI1TX \
|
|
|
|
|
0x00000800
|
|
|
|
|
#define UDMA_DEF_RESERVED_SEC_UART2RX \
|
|
|
|
|
0x00001000
|
|
|
|
|
#define UDMA_DEF_RESERVED_SEC_UART2TX \
|
|
|
|
|
0x00002000
|
|
|
|
|
#define UDMA_DEF_ADC00_SEC_TMR2A \
|
|
|
|
|
0x00004000
|
|
|
|
|
#define UDMA_DEF_ADC01_SEC_TMR2B \
|
|
|
|
|
0x00008000
|
|
|
|
|
#define UDMA_DEF_ADC02_SEC_RESERVED \
|
|
|
|
|
0x00010000
|
|
|
|
|
#define UDMA_DEF_ADC03_SEC_RESERVED \
|
|
|
|
|
0x00020000
|
|
|
|
|
#define UDMA_DEF_TMR0A_SEC_TMR1A \
|
|
|
|
|
0x00040000
|
|
|
|
|
#define UDMA_DEF_TMR0B_SEC_TMR1B \
|
|
|
|
|
0x00080000
|
|
|
|
|
#define UDMA_DEF_TMR1A_SEC_EPI0RX \
|
|
|
|
|
0x00100000
|
|
|
|
|
#define UDMA_DEF_TMR1B_SEC_EPI0TX \
|
|
|
|
|
0x00200000
|
|
|
|
|
#define UDMA_DEF_UART1RX_SEC_RESERVED \
|
|
|
|
|
0x00400000
|
|
|
|
|
#define UDMA_DEF_UART1TX_SEC_RESERVED \
|
|
|
|
|
0x00800000
|
|
|
|
|
#define UDMA_DEF_SSI1RX_SEC_ADC10 \
|
|
|
|
|
0x01000000
|
|
|
|
|
#define UDMA_DEF_SSI1TX_SEC_ADC11 \
|
|
|
|
|
0x02000000
|
|
|
|
|
#define UDMA_DEF_RESERVED_SEC_ADC12 \
|
|
|
|
|
0x04000000
|
|
|
|
|
#define UDMA_DEF_RESERVED_SEC_ADC13 \
|
|
|
|
|
0x08000000
|
|
|
|
|
#define UDMA_DEF_I2S0RX_SEC_RESERVED \
|
|
|
|
|
0x10000000
|
|
|
|
|
#define UDMA_DEF_I2S0TX_SEC_RESERVED \
|
|
|
|
|
0x20000000
|
|
|
|
|
|
2011-12-23 10:59:07 +08:00
|
|
|
//*****************************************************************************
|
|
|
|
|
//
|
|
|
|
|
// Values that can be passed to uDMAChannelMapConfigure() to select peripheral
|
|
|
|
|
// mapping for each channel. The channels named RESERVED may be assigned
|
|
|
|
|
// to a peripheral in future parts.
|
|
|
|
|
//
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
//
|
|
|
|
|
// Channel 0
|
|
|
|
|
//
|
|
|
|
|
#define UDMA_CH0_USB0EP1RX 0x00000000
|
|
|
|
|
#define UDMA_CH0_UART2RX 0x00010000
|
|
|
|
|
#define UDMA_CH0_RESERVED2 0x00020000
|
|
|
|
|
#define UDMA_CH0_TIMER4A 0x00030000
|
|
|
|
|
#define UDMA_CH0_RESERVED4 0x00040000
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Channel 1
|
|
|
|
|
//
|
|
|
|
|
#define UDMA_CH1_USB0EP1TX 0x00000001
|
|
|
|
|
#define UDMA_CH1_UART2TX 0x00010001
|
|
|
|
|
#define UDMA_CH1_RESERVED2 0x00020001
|
|
|
|
|
#define UDMA_CH1_TIMER4B 0x00030001
|
|
|
|
|
#define UDMA_CH1_RESERVED4 0x00040001
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Channel 2
|
|
|
|
|
//
|
|
|
|
|
#define UDMA_CH2_USB0EP2RX 0x00000002
|
|
|
|
|
#define UDMA_CH2_TIMER3A 0x00010002
|
|
|
|
|
#define UDMA_CH2_RESERVED2 0x00020002
|
|
|
|
|
#define UDMA_CH2_RESERVED3 0x00030002
|
|
|
|
|
#define UDMA_CH2_RESERVED4 0x00040002
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Channel 3
|
|
|
|
|
//
|
|
|
|
|
#define UDMA_CH3_USB0EP2TX 0x00000003
|
|
|
|
|
#define UDMA_CH3_TIMER3B 0x00010003
|
|
|
|
|
#define UDMA_CH3_RESERVED2 0x00020003
|
|
|
|
|
#define UDMA_CH3_LPC0_3 0x00030003
|
|
|
|
|
#define UDMA_CH3_RESERVED4 0x00040003
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Channel 4
|
|
|
|
|
//
|
|
|
|
|
#define UDMA_CH4_USB0EP3RX 0x00000004
|
|
|
|
|
#define UDMA_CH4_TIMER2A 0x00010004
|
|
|
|
|
#define UDMA_CH4_RESERVED2 0x00020004
|
|
|
|
|
#define UDMA_CH4_GPIOA 0x00030004
|
|
|
|
|
#define UDMA_CH4_RESERVED4 0x00040004
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Channel 5
|
|
|
|
|
//
|
|
|
|
|
#define UDMA_CH5_USB0EP3TX 0x00000005
|
|
|
|
|
#define UDMA_CH5_TIMER2B 0x00010005
|
|
|
|
|
#define UDMA_CH5_RESERVED2 0x00020005
|
|
|
|
|
#define UDMA_CH5_GPIOB 0x00030005
|
|
|
|
|
#define UDMA_CH5_RESERVED4 0x00040005
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Channel 6
|
|
|
|
|
//
|
|
|
|
|
#define UDMA_CH6_RESERVED0 0x00000006
|
|
|
|
|
#define UDMA_CH6_TIMER2A 0x00010006
|
|
|
|
|
#define UDMA_CH6_UART5RX 0x00020006
|
|
|
|
|
#define UDMA_CH6_GPIOC 0x00030006
|
|
|
|
|
#define UDMA_CH6_I2C0RX 0x00040006
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Channel 7
|
|
|
|
|
//
|
|
|
|
|
#define UDMA_CH7_RESERVED0 0x00000007
|
|
|
|
|
#define UDMA_CH7_TIMER2B 0x00010007
|
|
|
|
|
#define UDMA_CH7_UART5TX 0x00020007
|
|
|
|
|
#define UDMA_CH7_GPIOD 0x00030007
|
|
|
|
|
#define UDMA_CH7_I2C0TX 0x00040007
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Channel 8
|
|
|
|
|
//
|
|
|
|
|
#define UDMA_CH8_UART0RX 0x00000008
|
|
|
|
|
#define UDMA_CH8_UART1RX 0x00010008
|
|
|
|
|
#define UDMA_CH8_RESERVED2 0x00020008
|
|
|
|
|
#define UDMA_CH8_TIMER5A 0x00030008
|
|
|
|
|
#define UDMA_CH8_I2C1RX 0x00040008
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Channel 9
|
|
|
|
|
//
|
|
|
|
|
#define UDMA_CH9_UART0TX 0x00000009
|
|
|
|
|
#define UDMA_CH9_UART1TX 0x00010009
|
|
|
|
|
#define UDMA_CH9_RESERVED2 0x00020009
|
|
|
|
|
#define UDMA_CH9_TIMER5B 0x00030009
|
|
|
|
|
#define UDMA_CH9_I2C1TX 0x00040009
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Channel 10
|
|
|
|
|
//
|
|
|
|
|
#define UDMA_CH10_SSI0RX 0x0000000A
|
|
|
|
|
#define UDMA_CH10_SSI1RX 0x0001000A
|
|
|
|
|
#define UDMA_CH10_UART6RX 0x0002000A
|
|
|
|
|
#define UDMA_CH10_WTIMER0A 0x0003000A
|
|
|
|
|
#define UDMA_CH10_I2C2RX 0x0004000A
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Channel 11
|
|
|
|
|
//
|
|
|
|
|
#define UDMA_CH11_SSI0TX 0x0000000B
|
|
|
|
|
#define UDMA_CH11_SSI1TX 0x0001000B
|
|
|
|
|
#define UDMA_CH11_UART6TX 0x0002000B
|
|
|
|
|
#define UDMA_CH11_WTIMER0B 0x0003000B
|
|
|
|
|
#define UDMA_CH11_I2C2TX 0x0004000B
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Channel 12
|
|
|
|
|
//
|
|
|
|
|
#define UDMA_CH12_RESERVED0 0x0000000C
|
|
|
|
|
#define UDMA_CH12_UART2RX 0x0001000C
|
|
|
|
|
#define UDMA_CH12_SSI2RX 0x0002000C
|
|
|
|
|
#define UDMA_CH12_WTIMER1A 0x0003000C
|
|
|
|
|
#define UDMA_CH12_GPIOK 0x0004000C
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Channel 13
|
|
|
|
|
//
|
|
|
|
|
#define UDMA_CH13_RESERVED0 0x0000000D
|
|
|
|
|
#define UDMA_CH13_UART2TX 0x0001000D
|
|
|
|
|
#define UDMA_CH13_SSI2TX 0x0002000D
|
|
|
|
|
#define UDMA_CH13_WTIMER1B 0x0003000D
|
|
|
|
|
#define UDMA_CH13_GPIOL 0x0004000D
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Channel 14
|
|
|
|
|
//
|
|
|
|
|
#define UDMA_CH14_ADC0_0 0x0000000E
|
|
|
|
|
#define UDMA_CH14_TIMER2A 0x0001000E
|
|
|
|
|
#define UDMA_CH14_SSI3RX 0x0002000E
|
|
|
|
|
#define UDMA_CH14_GPIOE 0x0003000E
|
|
|
|
|
#define UDMA_CH14_GPIOM 0x0004000E
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Channel 15
|
|
|
|
|
//
|
|
|
|
|
#define UDMA_CH15_ADC0_1 0x0000000F
|
|
|
|
|
#define UDMA_CH15_TIMER2B 0x0001000F
|
|
|
|
|
#define UDMA_CH15_SSI3TX 0x0002000F
|
|
|
|
|
#define UDMA_CH15_GPIOF 0x0003000F
|
|
|
|
|
#define UDMA_CH15_GPION 0x0004000F
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Channel 16
|
|
|
|
|
//
|
|
|
|
|
#define UDMA_CH16_ADC0_2 0x00000010
|
|
|
|
|
#define UDMA_CH16_RESERVED1 0x00010010
|
|
|
|
|
#define UDMA_CH16_UART3RX 0x00020010
|
|
|
|
|
#define UDMA_CH16_WTIMER2A 0x00030010
|
|
|
|
|
#define UDMA_CH16_GPIOP 0x00040010
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Channel 17
|
|
|
|
|
//
|
|
|
|
|
#define UDMA_CH17_ADC0_3 0x00000011
|
|
|
|
|
#define UDMA_CH17_RESERVED1 0x00010011
|
|
|
|
|
#define UDMA_CH17_UART3TX 0x00020011
|
|
|
|
|
#define UDMA_CH17_WTIMER2B 0x00030011
|
|
|
|
|
#define UDMA_CH17_RESERVED4 0x00040011
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Channel 18
|
|
|
|
|
//
|
|
|
|
|
#define UDMA_CH18_TIMER0A 0x00000012
|
|
|
|
|
#define UDMA_CH18_TIMER1A 0x00010012
|
|
|
|
|
#define UDMA_CH18_UART4RX 0x00020012
|
|
|
|
|
#define UDMA_CH18_GPIOB 0x00030012
|
|
|
|
|
#define UDMA_CH18_I2C3RX 0x00040012
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Channel 19
|
|
|
|
|
//
|
|
|
|
|
#define UDMA_CH19_TIMER0B 0x00000013
|
|
|
|
|
#define UDMA_CH19_TIMER1B 0x00010013
|
|
|
|
|
#define UDMA_CH19_UART4TX 0x00020013
|
|
|
|
|
#define UDMA_CH19_GPIOG 0x00030013
|
|
|
|
|
#define UDMA_CH19_I2C3TX 0x00040013
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Channel 20
|
|
|
|
|
//
|
|
|
|
|
#define UDMA_CH20_TIMER1A 0x00000014
|
|
|
|
|
#define UDMA_CH20_RESERVED1 0x00010014
|
|
|
|
|
#define UDMA_CH20_UART7RX 0x00020014
|
|
|
|
|
#define UDMA_CH20_GPIOH 0x00030014
|
|
|
|
|
#define UDMA_CH20_I2C4RX 0x00040014
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Channel 21
|
|
|
|
|
//
|
|
|
|
|
#define UDMA_CH21_TIMER1B 0x00000015
|
|
|
|
|
#define UDMA_CH21_RESERVED1 0x00010015
|
|
|
|
|
#define UDMA_CH21_UART7TX 0x00020015
|
|
|
|
|
#define UDMA_CH21_GPIOJ 0x00030015
|
|
|
|
|
#define UDMA_CH21_I2C4TX 0x00040015
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Channel 22
|
|
|
|
|
//
|
|
|
|
|
#define UDMA_CH22_UART1RX 0x00000016
|
|
|
|
|
#define UDMA_CH22_RESERVED1 0x00010016
|
|
|
|
|
#define UDMA_CH22_RESERVED2 0x00020016
|
|
|
|
|
#define UDMA_CH22_LPC0_2 0x00030016
|
|
|
|
|
#define UDMA_CH22_I2C5RX 0x00040016
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Channel 23
|
|
|
|
|
//
|
|
|
|
|
#define UDMA_CH23_UART1TX 0x00000017
|
|
|
|
|
#define UDMA_CH23_RESERVED1 0x00010017
|
|
|
|
|
#define UDMA_CH23_RESERVED2 0x00020017
|
|
|
|
|
#define UDMA_CH23_LPC0_1 0x00030017
|
|
|
|
|
#define UDMA_CH23_I2C5TX 0x00040017
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//
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// Channel 24
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//
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#define UDMA_CH24_SSI1RX 0x00000018
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#define UDMA_CH24_ADC1_0 0x00010018
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#define UDMA_CH24_RESERVED2 0x00020018
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#define UDMA_CH24_WTIMER3A 0x00030018
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#define UDMA_CH24_GPIOQ 0x00040018
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//
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// Channel 25
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//
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#define UDMA_CH25_SSI1TX 0x00000019
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#define UDMA_CH25_ADC1_1 0x00010019
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#define UDMA_CH25_RESERVED2 0x00020019
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#define UDMA_CH25_WTIMER3B 0x00030019
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#define UDMA_CH25_RESERVED4 0x00040019
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//
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// Channel 26
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//
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#define UDMA_CH26_RESERVED0 0x0000001A
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#define UDMA_CH26_ADC1_2 0x0001001A
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#define UDMA_CH26_RESERVED2 0x0002001A
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#define UDMA_CH26_WTIMER4A 0x0003001A
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#define UDMA_CH26_RESERVED4 0x0004001A
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//
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// Channel 27
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//
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#define UDMA_CH27_RESERVED0 0x0000001B
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#define UDMA_CH27_ADC1_3 0x0001001B
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#define UDMA_CH27_RESERVED2 0x0002001B
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#define UDMA_CH27_WTIMER4B 0x0003001B
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#define UDMA_CH27_RESERVED4 0x0004001B
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//
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// Channel 28
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//
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#define UDMA_CH28_RESERVED0 0x0000001C
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#define UDMA_CH28_RESERVED1 0x0001001C
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#define UDMA_CH28_RESERVED2 0x0002001C
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#define UDMA_CH28_WTIMER5A 0x0003001C
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#define UDMA_CH28_RESERVED4 0x0004001C
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//
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// Channel 29
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//
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#define UDMA_CH29_RESERVED0 0x0000001D
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#define UDMA_CH29_RESERVED1 0x0001001D
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#define UDMA_CH29_RESERVED2 0x0002001D
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#define UDMA_CH29_WTIMER5B 0x0003001D
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#define UDMA_CH29_RESERVED4 0x0004001D
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|
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//
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// Channel 30
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|
|
//
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|
|
#define UDMA_CH30_SW 0x0000001E
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#define UDMA_CH30_RESERVED1 0x0001001E
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|
|
#define UDMA_CH30_RESERVED2 0x0002001E
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|
|
#define UDMA_CH30_RESERVED3 0x0003001E
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|
|
#define UDMA_CH30_RESERVED4 0x0004001E
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Channel 31
|
|
|
|
|
//
|
|
|
|
|
#define UDMA_CH31_RESERVED0 0x0000001F
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|
|
#define UDMA_CH31_RESERVED1 0x0001001F
|
|
|
|
|
#define UDMA_CH31_RESERVED2 0x0002001F
|
|
|
|
|
#define UDMA_CH31_LPC0_0 0x0003001F
|
|
|
|
|
#define UDMA_CH31_RESERVED4 0x0004001F
|
|
|
|
|
|
2011-06-23 08:47:34 +08:00
|
|
|
//*****************************************************************************
|
|
|
|
|
//
|
|
|
|
|
// API Function prototypes
|
|
|
|
|
//
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
extern void uDMAEnable(void);
|
|
|
|
|
extern void uDMADisable(void);
|
|
|
|
|
extern unsigned long uDMAErrorStatusGet(void);
|
|
|
|
|
extern void uDMAErrorStatusClear(void);
|
2011-12-23 10:59:07 +08:00
|
|
|
extern void uDMAChannelEnable(unsigned long ulChannelNum);
|
|
|
|
|
extern void uDMAChannelDisable(unsigned long ulChannelNum);
|
|
|
|
|
extern tBoolean uDMAChannelIsEnabled(unsigned long ulChannelNum);
|
2011-06-23 08:47:34 +08:00
|
|
|
extern void uDMAControlBaseSet(void *pControlTable);
|
|
|
|
|
extern void *uDMAControlBaseGet(void);
|
2011-12-23 10:59:07 +08:00
|
|
|
extern void *uDMAControlAlternateBaseGet(void);
|
|
|
|
|
extern void uDMAChannelRequest(unsigned long ulChannelNum);
|
|
|
|
|
extern void uDMAChannelAttributeEnable(unsigned long ulChannelNum,
|
2011-06-23 08:47:34 +08:00
|
|
|
unsigned long ulAttr);
|
2011-12-23 10:59:07 +08:00
|
|
|
extern void uDMAChannelAttributeDisable(unsigned long ulChannelNum,
|
2011-06-23 08:47:34 +08:00
|
|
|
unsigned long ulAttr);
|
2011-12-23 10:59:07 +08:00
|
|
|
extern unsigned long uDMAChannelAttributeGet(unsigned long ulChannelNum);
|
|
|
|
|
extern void uDMAChannelControlSet(unsigned long ulChannelStructIndex,
|
2011-06-23 08:47:34 +08:00
|
|
|
unsigned long ulControl);
|
2011-12-23 10:59:07 +08:00
|
|
|
extern void uDMAChannelTransferSet(unsigned long ulChannelStructIndex,
|
2011-06-23 08:47:34 +08:00
|
|
|
unsigned long ulMode, void *pvSrcAddr,
|
|
|
|
|
void *pvDstAddr,
|
|
|
|
|
unsigned long ulTransferSize);
|
2011-12-23 10:59:07 +08:00
|
|
|
extern void uDMAChannelScatterGatherSet(unsigned long ulChannelNum,
|
|
|
|
|
unsigned ulTaskCount, void *pvTaskList,
|
|
|
|
|
unsigned long ulIsPeriphSG);
|
|
|
|
|
extern unsigned long uDMAChannelSizeGet(unsigned long ulChannelStructIndex);
|
|
|
|
|
extern unsigned long uDMAChannelModeGet(unsigned long ulChannelStructIndex);
|
2011-06-23 08:47:34 +08:00
|
|
|
extern void uDMAIntRegister(unsigned long ulIntChannel,
|
|
|
|
|
void (*pfnHandler)(void));
|
|
|
|
|
extern void uDMAIntUnregister(unsigned long ulIntChannel);
|
|
|
|
|
extern void uDMAChannelSelectDefault(unsigned long ulDefPeriphs);
|
|
|
|
|
extern void uDMAChannelSelectSecondary(unsigned long ulSecPeriphs);
|
2011-12-23 10:59:07 +08:00
|
|
|
extern unsigned long uDMAIntStatus(void);
|
|
|
|
|
extern void uDMAIntClear(unsigned long ulChanMask);
|
|
|
|
|
extern void uDMAChannelAssign(unsigned long ulMapping);
|
2011-06-23 08:47:34 +08:00
|
|
|
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
//
|
|
|
|
|
// Mark the end of the C bindings section for C++ compilers.
|
|
|
|
|
//
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
#ifdef __cplusplus
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
2011-12-23 10:59:07 +08:00
|
|
|
#endif // __UDMA_H__
|
