128 lines
5.8 KiB
C
128 lines
5.8 KiB
C
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/*
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* Copyright (c) 2013 Nuvoton Technology Corp.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* Description: NUC472 EMAC driver header file
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*/
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#include "lwip/def.h"
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#include "lwip/pbuf.h"
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#include "NUC472_442.h"
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#ifndef _NUC472_ETH_
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#define _NUC472_ETH_
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/* Generic MII registers. */
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#define MII_BMCR 0x00 /* Basic mode control register */
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#define MII_BMSR 0x01 /* Basic mode status register */
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#define MII_PHYSID1 0x02 /* PHYS ID 1 */
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#define MII_PHYSID2 0x03 /* PHYS ID 2 */
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#define MII_ADVERTISE 0x04 /* Advertisement control reg */
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#define MII_LPA 0x05 /* Link partner ability reg */
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#define MII_EXPANSION 0x06 /* Expansion register */
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#define MII_DCOUNTER 0x12 /* Disconnect counter */
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#define MII_FCSCOUNTER 0x13 /* False carrier counter */
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#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
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#define MII_RERRCOUNTER 0x15 /* Receive error counter */
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#define MII_SREVISION 0x16 /* Silicon revision */
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#define MII_RESV1 0x17 /* Reserved... */
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#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
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#define MII_PHYADDR 0x19 /* PHY address */
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#define MII_RESV2 0x1a /* Reserved... */
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#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
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#define MII_NCONFIG 0x1c /* Network interface config */
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/* Basic mode control register. */
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#define BMCR_RESV 0x007f /* Unused... */
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#define BMCR_CTST 0x0080 /* Collision test */
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#define BMCR_FULLDPLX 0x0100 /* Full duplex */
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#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
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#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
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#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
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#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
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#define BMCR_SPEED100 0x2000 /* Select 100Mbps */
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#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
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#define BMCR_RESET 0x8000 /* Reset the DP83840 */
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/* Basic mode status register. */
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#define BMSR_ERCAP 0x0001 /* Ext-reg capability */
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#define BMSR_JCD 0x0002 /* Jabber detected */
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#define BMSR_LSTATUS 0x0004 /* Link status */
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#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
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#define BMSR_RFAULT 0x0010 /* Remote fault detected */
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#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
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#define BMSR_RESV 0x07c0 /* Unused... */
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#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
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#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
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#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
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#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
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#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
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/* Advertisement control register. */
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#define ADVERTISE_SLCT 0x001f /* Selector bits */
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#define ADVERTISE_CSMA 0x0001 /* Only selector supported */
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#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
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#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
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#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
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#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
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#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
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#define ADVERTISE_RESV 0x1c00 /* Unused... */
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#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
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#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
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#define ADVERTISE_NPAGE 0x8000 /* Next page bit */
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#define RX_DESCRIPTOR_NUM 4 // Max Number of Rx Frame Descriptors
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#define TX_DESCRIPTOR_NUM 2 // Max number of Tx Frame Descriptors
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#define PACKET_BUFFER_SIZE 1520
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#define CONFIG_PHY_ADDR 1
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// Frame Descriptor's Owner bit
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#define OWNERSHIP_EMAC 0x80000000 // 1 = EMAC
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//#define OWNERSHIP_CPU 0x7fffffff // 0 = CPU
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// Rx Frame Descriptor Status
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#define RXFD_RXGD 0x00100000 // Receiving Good Packet Received
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#define RXFD_RTSAS 0x00800000 // RX Time Stamp Available
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// Tx Frame Descriptor's Control bits
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#define TXFD_TTSEN 0x08 // Tx Time Stamp Enable
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#define TXFD_INTEN 0x04 // Interrupt Enable
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#define TXFD_CRCAPP 0x02 // Append CRC
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#define TXFD_PADEN 0x01 // Padding Enable
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// Tx Frame Descriptor Status
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#define TXFD_TXCP 0x00080000 // Transmission Completion
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#define TXFD_TTSAS 0x08000000 // TX Time Stamp Available
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// Tx/Rx buffer descriptor structure
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struct eth_descriptor {
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u32_t status1;
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u8_t *buf;
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u32_t status2;
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struct eth_descriptor *next;
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};
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#endif /* _NUC472_ETH_ */
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