636 lines
16 KiB
C
636 lines
16 KiB
C
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/*
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* File : board_spi_master.h
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2015-11-19 Urey the first version
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*/
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#ifndef DRV_SPI_H__
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#define DRV_SPI_H__
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#include <rtthread.h>
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#include <rtdevice.h>
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#include "board.h"
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#include "drv_gpio.h"
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/* SSI REGISTER */
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#define SSI_DR 0x00
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#define SSI_CR0 0x04
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#define SSI_CR1 0x08
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#define SSI_SR 0x0C
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#define SSI_ITR 0x10
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#define SSI_ICR 0x14
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#define SSI_GR 0x18
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/* SSI Data Register (SSI_DR) */
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#define DR_GPC_BIT 0
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#define DR_GPC_MASK (0x1ff << SSI_DR_GPC_BIT)
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/* SSI Control Register 0 (SSI_CR0) */
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#define CR0_TENDIAN_BIT 18
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#define CR0_TENDIAN_MASK (3 << CR0_TENDIAN_BIT)
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#define CR0_RENDIAN_BIT 16
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#define CR0_RENDIAN_MASK (3 << CR0_RENDIAN_BIT)
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#define CR0_SSIE (1 << 15)
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#define CR0_TIE (1 << 14)
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#define CR0_RIE (1 << 13)
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#define CR0_TEIE (1 << 12)
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#define CR0_REIE (1 << 11)
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#define CR0_LOOP (1 << 10)
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#define CR0_RFINE (1 << 9)
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#define CR0_RFINC (1 << 8)
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#define CR0_EACLRUN (1 << 7) /* hardware auto clear underrun when TxFifo no empty */
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#define CR0_FSEL (1 << 6)
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#define CR0_VRCNT (1 << 4)
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#define CR0_TFMODE (1 << 3)
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#define CR0_TFLUSH (1 << 2)
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#define CR0_RFLUSH (1 << 1)
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#define CR0_DISREV (1 << 0)
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/* SSI Control Register 1 (SSI_CR1) */
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#define CR1_FRMHL_BIT 30
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#define CR1_FRMHL_MASK (0x3 << CR1_FRMHL_BIT)
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#define CR1_FRMHL_CELOW_CE2LOW (0 << CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is low valid */
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#define CR1_FRMHL_CEHIGH_CE2LOW (1 << CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is low valid */
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#define CR1_FRMHL_CELOW_CE2HIGH (2 << CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is high valid */
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#define CR1_FRMHL_CEHIGH_CE2HIGH (3 << CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is high valid */
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#define CR1_TFVCK_BIT 28
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#define CR1_TFVCK_MASK (0x3 << CR1_TFVCK_BIT)
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#define CR1_TFVCK_0 (0 << CR1_TFVCK_BIT)
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#define CR1_TFVCK_1 (1 << CR1_TFVCK_BIT)
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#define CR1_TFVCK_2 (2 << CR1_TFVCK_BIT)
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#define CR1_TFVCK_3 (3 << CR1_TFVCK_BIT)
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#define CR1_TCKFI_BIT 26
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#define CR1_TCKFI_MASK (0x3 << CR1_TCKFI_BIT)
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#define CR1_TCKFI_0 (0 << CR1_TCKFI_BIT)
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#define CR1_TCKFI_1 (1 << CR1_TCKFI_BIT)
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#define CR1_TCKFI_2 (2 << CR1_TCKFI_BIT)
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#define CR1_TCKFI_3 (3 << CR1_TCKFI_BIT)
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#define CR1_ITFRM (1 << 24)
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#define CR1_UNFIN (1 << 23)
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#define CR1_FMAT_BIT 20
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#define CR1_FMAT_MASK (0x3 << CR1_FMAT_BIT)
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#define CR1_FMAT_SPI (0 << CR1_FMAT_BIT) /* Motorola¡¯s SPI format */
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#define CR1_FMAT_SSP (1 << CR1_FMAT_BIT) /* TI's SSP format */
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#define CR1_FMAT_MW1 (2 << CR1_FMAT_BIT) /* National Microwire 1 format */
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#define CR1_FMAT_MW2 (3 << CR1_FMAT_BIT) /* National Microwire 2 format */
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#define CR1_TTRG_BIT 16 /* SSI1 TX trigger */
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#define CR1_TTRG_MASK (0xf << CR1_TTRG_BIT)
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#define CR1_MCOM_BIT 12
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#define CR1_MCOM_MASK (0xf << CR1_MCOM_BIT)
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// #define CR1_MCOM_BIT(NO) (##NO## << CR1_MCOM_BIT) /* N-bit command selected */
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#define CR1_RTRG_BIT 8 /* SSI RX trigger */
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#define CR1_RTRG_MASK (0xf << CR1_RTRG_BIT)
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#define CR1_FLEN_BIT 3
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#define CR1_FLEN_MASK (0x1f << CR1_FLEN_BIT)
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#define CR1_FLEN_2BIT (0x0 << CR1_FLEN_BIT)
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#define CR1_PHA (1 << 1)
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#define CR1_POL (1 << 0)
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/* SSI Status Register (SSI_SR) */
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#define SR_TFIFONUM_BIT 16
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#define SR_TFIFONUM_MASK (0xff << SR_TFIFONUM_BIT)
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#define SR_RFIFONUM_BIT 8
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#define SR_RFIFONUM_MASK (0xff << SR_RFIFONUM_BIT)
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#define SR_END (1 << 7)
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#define SR_BUSY (1 << 6)
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#define SR_TFF (1 << 5)
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#define SR_RFE (1 << 4)
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#define SR_TFHE (1 << 3)
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#define SR_RFHF (1 << 2)
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#define SR_UNDR (1 << 1)
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#define SR_OVER (1 << 0)
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/* SSI Interval Time Control Register (SSI_ITR) */
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#define ITR_CNTCLK (1 << 15)
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#define ITR_IVLTM_BIT 0
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#define ITR_IVLTM_MASK (0x7fff << ITR_IVLTM_BIT)
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#define R_MODE 0x1
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#define W_MODE 0x2
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#define RW_MODE (R_MODE | W_MODE)
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#define R_DMA 0x4
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#define W_DMA 0x8
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#define RW_DMA (R_DMA |W_DMA)
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#define SPI_DMA_ACK 0x1
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#define SPI_DMA_ERROR -3
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#define SPI_CPU_ERROR -4
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#define SPI_COMPLETE 5
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#define JZ_SSI_MAX_FIFO_ENTRIES 128
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#define JZ_SSI_DMA_BURST_LENGTH 16
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#define FIFO_W8 8
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#define FIFO_W16 16
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#define FIFO_W32 32
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#define SPI_BITS_8 8
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#define SPI_BITS_16 16
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#define SPI_BITS_32 32
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#define SPI_8BITS 1
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#define SPI_16BITS 2
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#define SPI_32BITS 4
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/* tx rx threshold from 0x0 to 0xF */
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#define SSI_FULL_THRESHOLD 0xF
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#define SSI_TX_FIFO_THRESHOLD 0x1
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#define SSI_RX_FIFO_THRESHOLD (SSI_FULL_THRESHOLD - SSI_TX_FIFO_THRESHOLD)
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#define SSI_SAFE_THRESHOLD 0x1
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#define CPU_ONCE_BLOCK_ENTRIES ((SSI_FULL_THRESHOLD-SSI_TX_FIFO_THRESHOLD)*8)
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#define MAX_SSI_INTR 10000
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#define MAX_SSICDR 63
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#define MAX_CGV 255
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#define SSI_DMA_FASTNESS_CHNL 0 // SSI controller [n] FASTNESS when probe();
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#define JZ_NEW_CODE_TYPE
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#define BUFFER_SIZE PAGE_SIZE
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#define CONFIG_DMA_ENGINE 1
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#define SUSPND (1<<0)
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#define SPIBUSY (1<<1)
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#define RXBUSY (1<<2)
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#define TXBUSY (1<<3)
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struct jz_spi_rx_fifo
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{
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/* software fifo */
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rt_uint8_t *buffer;
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rt_uint16_t put_index, get_index;
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};
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struct jz_spi_tx_fifo
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{
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struct rt_completion completion;
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};
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struct jz_spi_rx_dma
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{
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rt_bool_t activated;
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};
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struct jz_spi_tx_dma
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{
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rt_bool_t activated;
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struct rt_data_queue data_queue;
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};
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typedef struct jz_spi
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{
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struct rt_spi_bus parent;
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// struct rt_semaphore spi_done_sem;
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struct rt_completion completion;
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struct clk *clk;
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struct clk *clk_gate;
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uint32_t base;
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uint8_t is_first;
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uint8_t xfer_unit_size; /* 1,2,4 */
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uint32_t totalCount;
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uint32_t sendCount;
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uint32_t recvCount;
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uint8_t tx_trigger; /* 0-128 */
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uint8_t rx_trigger; /* 0-128 */
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uint8_t *rx_buf;
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uint8_t *tx_buf;
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uint32_t (*rx_func)(struct jz_spi *);
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uint32_t (*tx_func)(struct jz_spi *);
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}jz_spi_bus_t;
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struct jz_spi_cs
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{
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enum gpio_port port;
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enum gpio_pin pin;
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};
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static uint32_t spi_readl(struct jz_spi *spi_bus,uint32_t offset)
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{
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return readl(spi_bus->base + offset);
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}
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static void spi_writel(struct jz_spi *spi_bus, uint32_t offset,uint32_t value)
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{
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writel(value, spi_bus->base + offset);
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}
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static inline void spi_set_frmhl(struct jz_spi *spi, unsigned int frmhl)
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{
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u32 tmp;
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tmp = spi_readl(spi, SSI_CR1);
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tmp = (tmp & ~CR1_FRMHL_MASK) | frmhl;
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spi_writel(spi, SSI_CR1, tmp);
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}
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static inline void spi_set_clock_phase(struct jz_spi *spi, unsigned int cpha)
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{
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u32 tmp;
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tmp = spi_readl(spi, SSI_CR1);
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tmp = (tmp & ~CR1_PHA) | (cpha ? CR1_PHA : 0);
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spi_writel(spi, SSI_CR1, tmp);
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}
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static inline void spi_set_clock_polarity(struct jz_spi *spi, unsigned int cpol)
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{
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u32 tmp;
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tmp = spi_readl(spi, SSI_CR1);
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tmp = (tmp & ~CR1_POL) | (cpol ? CR1_POL : 0);
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spi_writel(spi, SSI_CR1, tmp);
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}
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static inline void spi_set_tx_msb(struct jz_spi *spi)
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{
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u32 tmp;
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tmp = spi_readl(spi, SSI_CR0);
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tmp &= ~CR0_TENDIAN_MASK;
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spi_writel(spi, SSI_CR0, tmp);
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}
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static inline void spi_set_tx_lsb(struct jz_spi *spi)
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{
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u32 tmp;
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tmp = spi_readl(spi, SSI_CR0);
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tmp |= (tmp & ~CR0_TENDIAN_MASK) | (0x3 << CR0_TENDIAN_BIT);
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spi_writel(spi, SSI_CR0, tmp);
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}
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static inline void spi_set_rx_msb(struct jz_spi *spi)
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{
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u32 tmp;
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tmp = spi_readl(spi, SSI_CR0);
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tmp &= ~CR0_RENDIAN_MASK;
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spi_writel(spi, SSI_CR0, tmp);
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}
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static inline void spi_set_rx_lsb(struct jz_spi *spi)
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{
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u32 tmp;
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tmp = spi_readl(spi, SSI_CR0);
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tmp |= (tmp & ~CR0_RENDIAN_MASK) | (0x3 << CR0_RENDIAN_BIT);
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spi_writel(spi, SSI_CR0, tmp);
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}
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static inline void spi_enable_loopback(struct jz_spi *spi)
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{
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u32 tmp;
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tmp = spi_readl(spi, SSI_CR0);
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tmp |= CR0_LOOP;
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spi_writel(spi, SSI_CR0, tmp);
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}
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static inline void spi_disable_loopback(struct jz_spi *spi)
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{
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u32 tmp;
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tmp = spi_readl(spi, SSI_CR0);
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tmp &= ~CR0_LOOP;
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spi_writel(spi, SSI_CR0, tmp);
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}
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static inline void spi_set_frame_length(struct jz_spi *spi, u32 len)
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{
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u32 tmp;
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tmp = spi_readl(spi, SSI_CR1);
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tmp = (tmp & ~CR1_FLEN_MASK) | (((len) - 2) << CR1_FLEN_BIT);
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spi_writel(spi, SSI_CR1, tmp);
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}
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static inline void spi_set_tx_trigger(struct jz_spi *spi, u32 val)
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{
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u32 tmp;
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tmp = spi_readl(spi, SSI_CR1);
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tmp = (tmp & ~CR1_TTRG_MASK) | ((val)/8) << CR1_TTRG_BIT;
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spi_writel(spi, SSI_CR1, tmp);
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}
|
||
|
|
|
||
|
|
static inline void spi_set_rx_trigger(struct jz_spi *spi, u32 val)
|
||
|
|
{
|
||
|
|
u32 tmp;
|
||
|
|
tmp = spi_readl(spi, SSI_CR1);
|
||
|
|
tmp = (tmp & ~CR1_RTRG_MASK) | ((val)/8) << CR1_RTRG_BIT;
|
||
|
|
spi_writel(spi, SSI_CR1, tmp);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void spi_enable_txfifo_half_empty_intr(struct jz_spi *spi)
|
||
|
|
{
|
||
|
|
u32 tmp;
|
||
|
|
tmp = spi_readl(spi, SSI_CR0);
|
||
|
|
tmp |= CR0_TIE;
|
||
|
|
spi_writel(spi, SSI_CR0, tmp);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void spi_disable_txfifo_half_empty_intr(struct jz_spi *spi)
|
||
|
|
{
|
||
|
|
u32 tmp;
|
||
|
|
tmp = spi_readl(spi, SSI_CR0);
|
||
|
|
tmp &= ~CR0_TIE;
|
||
|
|
spi_writel(spi, SSI_CR0, tmp);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void spi_enable_rxfifo_half_full_intr(struct jz_spi *spi)
|
||
|
|
{
|
||
|
|
u32 tmp;
|
||
|
|
tmp = spi_readl(spi, SSI_CR0);
|
||
|
|
tmp |= CR0_RIE;
|
||
|
|
spi_writel(spi, SSI_CR0, tmp);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void spi_disable_rxfifo_half_full_intr(struct jz_spi *spi)
|
||
|
|
{
|
||
|
|
u32 tmp;
|
||
|
|
tmp = spi_readl(spi, SSI_CR0);
|
||
|
|
tmp &= ~CR0_RIE;
|
||
|
|
spi_writel(spi, SSI_CR0, tmp);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void spi_enable_tx_intr(struct jz_spi *spi)
|
||
|
|
{
|
||
|
|
u32 tmp;
|
||
|
|
tmp = spi_readl(spi, SSI_CR0);
|
||
|
|
tmp |= CR0_TIE | CR0_TEIE;
|
||
|
|
spi_writel(spi, SSI_CR0, tmp);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void spi_disable_tx_intr(struct jz_spi *spi)
|
||
|
|
{
|
||
|
|
u32 tmp;
|
||
|
|
tmp = spi_readl(spi, SSI_CR0);
|
||
|
|
tmp &= ~(CR0_TIE | CR0_TEIE);
|
||
|
|
spi_writel(spi, SSI_CR0, tmp);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void spi_enable_rx_intr(struct jz_spi *spi)
|
||
|
|
{
|
||
|
|
u32 tmp;
|
||
|
|
tmp = spi_readl(spi, SSI_CR0);
|
||
|
|
tmp |= CR0_RIE | CR0_REIE;
|
||
|
|
spi_writel(spi, SSI_CR0, tmp);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void spi_disable_rx_intr(struct jz_spi *spi)
|
||
|
|
{
|
||
|
|
u32 tmp;
|
||
|
|
tmp = spi_readl(spi, SSI_CR0);
|
||
|
|
tmp &= ~(CR0_RIE | CR0_REIE);
|
||
|
|
spi_writel(spi, SSI_CR0, tmp);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void spi_enable_tx_error_intr(struct jz_spi *spi)
|
||
|
|
{
|
||
|
|
u32 tmp;
|
||
|
|
tmp = spi_readl(spi, SSI_CR0);
|
||
|
|
tmp |= CR0_TEIE;
|
||
|
|
spi_writel(spi, SSI_CR0, tmp);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void spi_disable_tx_error_intr(struct jz_spi *spi)
|
||
|
|
{
|
||
|
|
u32 tmp;
|
||
|
|
tmp = spi_readl(spi, SSI_CR0);
|
||
|
|
tmp &= ~CR0_TEIE;
|
||
|
|
spi_writel(spi, SSI_CR0, tmp);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void spi_enable_rx_error_intr(struct jz_spi *spi)
|
||
|
|
{
|
||
|
|
u32 tmp;
|
||
|
|
tmp = spi_readl(spi, SSI_CR0);
|
||
|
|
tmp |= CR0_REIE;
|
||
|
|
spi_writel(spi, SSI_CR0, tmp);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void spi_disable_rx_error_intr(struct jz_spi *spi)
|
||
|
|
{
|
||
|
|
u32 tmp;
|
||
|
|
tmp = spi_readl(spi, SSI_CR0);
|
||
|
|
tmp &= ~CR0_REIE;
|
||
|
|
spi_writel(spi, SSI_CR0, tmp);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void spi_underrun_auto_clear(struct jz_spi *spi)
|
||
|
|
{
|
||
|
|
u32 tmp;
|
||
|
|
tmp = spi_readl(spi, SSI_CR0);
|
||
|
|
tmp |= CR0_EACLRUN;
|
||
|
|
spi_writel(spi, SSI_CR0, tmp);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void spi_clear_errors(struct jz_spi *spi)
|
||
|
|
{
|
||
|
|
u32 tmp;
|
||
|
|
tmp = spi_readl(spi, SSI_SR);
|
||
|
|
tmp &= ~(SR_UNDR | SR_OVER);
|
||
|
|
spi_writel(spi, SSI_SR, tmp);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void spi_set_format(struct jz_spi *spi)
|
||
|
|
{
|
||
|
|
u32 tmp;
|
||
|
|
tmp = spi_readl(spi, SSI_CR1);
|
||
|
|
tmp &= ~CR1_FMAT_MASK;
|
||
|
|
tmp |= CR1_FMAT_SPI;
|
||
|
|
tmp &= ~(CR1_TFVCK_MASK | CR1_TCKFI_MASK);
|
||
|
|
tmp |= (CR1_TFVCK_0 | CR1_TCKFI_0);
|
||
|
|
// tmp |= (CR1_TFVCK_1 | CR1_TCKFI_1);
|
||
|
|
// tmp |= (CR1_TFVCK_2 | CR1_TCKFI_2);
|
||
|
|
// tmp |= (CR1_TFVCK_3 | CR1_TCKFI_3);
|
||
|
|
spi_writel(spi, SSI_CR1, tmp);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void spi_enable_receive(struct jz_spi *spi)
|
||
|
|
{
|
||
|
|
u32 tmp;
|
||
|
|
tmp = spi_readl(spi, SSI_CR0);
|
||
|
|
tmp &= ~CR0_DISREV;
|
||
|
|
spi_writel(spi, SSI_CR0, tmp);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void spi_disable_receive(struct jz_spi *spi)
|
||
|
|
{
|
||
|
|
u32 tmp;
|
||
|
|
tmp = spi_readl(spi, SSI_CR0);
|
||
|
|
tmp |= CR0_DISREV;
|
||
|
|
spi_writel(spi, SSI_CR0, tmp);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void spi_flush_fifo(struct jz_spi *spi)
|
||
|
|
{
|
||
|
|
u32 tmp;
|
||
|
|
tmp = spi_readl(spi, SSI_CR0);
|
||
|
|
tmp |= CR0_TFLUSH | CR0_RFLUSH;
|
||
|
|
spi_writel(spi, SSI_CR0, tmp);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void spi_finish_transmit(struct jz_spi *spi)
|
||
|
|
{
|
||
|
|
u32 tmp;
|
||
|
|
tmp = spi_readl(spi, SSI_CR1);
|
||
|
|
tmp &= ~CR1_UNFIN;
|
||
|
|
spi_writel(spi, SSI_CR1, tmp);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void spi_start_transmit(struct jz_spi *spi)
|
||
|
|
{
|
||
|
|
u32 tmp;
|
||
|
|
tmp = spi_readl(spi, SSI_CR1);
|
||
|
|
tmp |= CR1_UNFIN;
|
||
|
|
spi_writel(spi, SSI_CR1, tmp);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int spi_is_rxfifo_empty(struct jz_spi *spi)
|
||
|
|
{
|
||
|
|
return spi_readl(spi, SSI_SR) & SR_RFE;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int spi_check_busy(struct jz_spi *spi)
|
||
|
|
{
|
||
|
|
return spi_readl(spi, SSI_SR) & SR_BUSY;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void spi_disable(struct jz_spi *spi)
|
||
|
|
{
|
||
|
|
u32 tmp;
|
||
|
|
tmp = spi_readl(spi, SSI_CR0);
|
||
|
|
tmp &= ~CR0_SSIE;
|
||
|
|
spi_writel(spi, SSI_CR0, tmp);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void spi_enable(struct jz_spi *spi)
|
||
|
|
{
|
||
|
|
u32 tmp;
|
||
|
|
tmp = spi_readl(spi, SSI_CR0);
|
||
|
|
tmp |= CR0_SSIE;
|
||
|
|
spi_writel(spi, SSI_CR0, tmp);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline u32 spi_get_rxfifo_count(struct jz_spi *spi)
|
||
|
|
{
|
||
|
|
return (spi_readl(spi, SSI_SR) & SR_RFIFONUM_MASK) >> SR_RFIFONUM_BIT;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void spi_flush_txfifo(struct jz_spi *spi)
|
||
|
|
{
|
||
|
|
u32 tmp;
|
||
|
|
tmp = spi_readl(spi, SSI_CR0);
|
||
|
|
tmp |= CR0_TFLUSH;
|
||
|
|
spi_writel(spi, SSI_CR0, tmp);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void spi_flush_rxfifo(struct jz_spi *spi)
|
||
|
|
{
|
||
|
|
u32 tmp;
|
||
|
|
tmp = spi_readl(spi, SSI_CR0);
|
||
|
|
tmp |= CR0_RFLUSH;
|
||
|
|
spi_writel(spi, SSI_CR0, tmp);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int spi_get_underrun(struct jz_spi *spi)
|
||
|
|
{
|
||
|
|
return spi_readl(spi, SSI_SR) & SR_UNDR;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int spi_get_overrun(struct jz_spi *spi)
|
||
|
|
{
|
||
|
|
return spi_readl(spi, SSI_SR) & SR_OVER;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int spi_get_transfer_end(struct jz_spi *spi)
|
||
|
|
{
|
||
|
|
return spi_readl(spi, SSI_SR) & SR_END;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int spi_get_tx_error_intr(struct jz_spi *spi)
|
||
|
|
{
|
||
|
|
return spi_readl(spi, SSI_CR0) & CR0_TEIE;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int spi_get_rx_error_intr(struct jz_spi *spi)
|
||
|
|
{
|
||
|
|
return spi_readl(spi, SSI_CR0) & CR0_REIE;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int spi_get_rxfifo_half_full(struct jz_spi *spi)
|
||
|
|
{
|
||
|
|
return spi_readl(spi, SSI_SR) & SR_RFHF;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int spi_get_txfifo_half_empty(struct jz_spi *spi)
|
||
|
|
{
|
||
|
|
return spi_readl(spi, SSI_SR) & SR_TFHE;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int spi_get_txfifo_half_empty_intr(struct jz_spi *spi)
|
||
|
|
{
|
||
|
|
return spi_readl(spi, SSI_CR0) & CR0_TIE;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int spi_get_rxfifo_half_full_intr(struct jz_spi *spi)
|
||
|
|
{
|
||
|
|
return spi_readl(spi, SSI_CR0) & CR0_RIE;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void spi_select_ce0(struct jz_spi *spi)
|
||
|
|
{
|
||
|
|
u32 tmp;
|
||
|
|
tmp = spi_readl(spi, SSI_CR0);
|
||
|
|
tmp &= ~CR0_FSEL;
|
||
|
|
spi_writel(spi, SSI_CR0, tmp);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void spi_select_ce1(struct jz_spi *spi)
|
||
|
|
{
|
||
|
|
u32 tmp;
|
||
|
|
tmp = spi_readl(spi, SSI_CR0);
|
||
|
|
tmp |= CR0_FSEL;
|
||
|
|
spi_writel(spi, SSI_CR0, tmp);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void spi_send_data(struct jz_spi *spi, u32 value)
|
||
|
|
{
|
||
|
|
spi_writel(spi, SSI_DR, value);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* the spi->mode bits understood by this driver: */
|
||
|
|
#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST | SPI_LOOP)
|
||
|
|
#define SPI_BITS_SUPPORT (SPI_BITS_8 | SPI_BITS_16 | SPI_BITS_32)
|
||
|
|
|
||
|
|
#endif /* _SPI_MASTER_H_ */
|