220 lines
7.8 KiB
C
220 lines
7.8 KiB
C
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/*
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* Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*!
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* @file imx_uart.c
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* @brief UART driver.
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* @ingroup diag_uart
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*/
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#include "sdk.h"
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#include "registers/regsuart.h"
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#include "imx_uart.h"
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#include "ccm_pll.h"
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#include "interrupt.h"
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#define UART_UFCR_RFDIV BF_UART_UFCR_RFDIV(4)
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//#define UART_UFCR_RFDIV UART_UFCR_RFDIV_4
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//#define UART_UFCR_RFDIV UART_UFCR_RFDIV_7
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uint32_t uart_get_reffreq(uint32_t instance)
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{
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uint32_t div = UART_UFCR_RFDIV;
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uint32_t ret = 0;
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uint32_t freq = get_peri_clock(UART_MODULE_CLK(instance));
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if (div == BF_UART_UFCR_RFDIV(4))
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ret = freq / 2;
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else if (div == BF_UART_UFCR_RFDIV(2))
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ret = freq / 4;
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else if (div == BF_UART_UFCR_RFDIV(6))
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ret = freq / 7;
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return ret;
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}
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uint8_t uart_putchar(uint32_t instance, uint8_t * ch)
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{
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/* Wait for Tx FIFO not full */
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while (HW_UART_UTS(instance).B.TXFULL);
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HW_UART_UTXD_WR(instance, *ch);
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return *ch;
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}
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uint8_t uart_getchar(uint32_t instance)
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{
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uint32_t read_data;
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/* If Rx FIFO has no data ready */
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if (!(HW_UART_USR2(instance).B.RDR))
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return NONE_CHAR;
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read_data = HW_UART_URXD_RD(instance);
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/* If error are detected */
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if (read_data & 0x7C00)
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return NONE_CHAR;
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return (uint8_t) read_data;
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}
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void uart_set_FIFO_mode(uint32_t instance, uint8_t fifo, uint8_t trigger_level,
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uint8_t service_mode)
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{
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if (fifo == TX_FIFO) {
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/* Configure the TX_FIFO trigger level */
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HW_UART_UFCR_CLR(instance,BM_UART_UFCR_TXTL);
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HW_UART_UFCR_SET(instance, BF_UART_UFCR_TXTL(trigger_level));
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/* Configure the TX_FIFO service mode */
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/* Default mode is polling: IRQ and DMA requests are disabled */
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HW_UART_UCR1_CLR(instance,(BM_UART_UCR1_TRDYEN | BM_UART_UCR1_TXDMAEN));
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if (service_mode == DMA_MODE)
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HW_UART_UCR1_SET(instance,BM_UART_UCR1_TXDMAEN);
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else if (service_mode == IRQ_MODE)
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HW_UART_UCR1_SET(instance,BM_UART_UCR1_TRDYEN);
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} else { /* fifo = RX_FIFO */
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/* Configure the RX_FIFO trigger level */
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HW_UART_UFCR_CLR(instance,BM_UART_UFCR_RXTL);
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HW_UART_UFCR_SET(instance,BF_UART_UFCR_RXTL(trigger_level));
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/* Configure the RX_FIFO service mode */
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/* Default mode is polling: IRQ and DMA requests are disabled */
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HW_UART_UCR1_CLR(instance,(BM_UART_UCR1_RRDYEN | BM_UART_UCR1_RXDMAEN));
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if (service_mode == DMA_MODE)
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HW_UART_UCR1_SET(instance,BM_UART_UCR1_RXDMAEN);
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else if (service_mode == IRQ_MODE)
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HW_UART_UCR1_SET(instance,BM_UART_UCR1_RRDYEN);
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}
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}
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void uart_set_loopback_mode(uint32_t instance, uint8_t state)
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{
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if (state == TRUE)
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HW_UART_UTS_SET(instance, BM_UART_UTS_LOOP);
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else
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HW_UART_UTS_CLR(instance, BM_UART_UTS_LOOP);
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}
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void uart_setup_interrupt(uint32_t instance, void (*irq_subroutine)(void), uint8_t state)
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{
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uint32_t irq_id = UART_IRQS(instance);
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if (state == TRUE) {
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/* register the IRQ sub-routine */
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register_interrupt_routine(irq_id, irq_subroutine);
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/* enable the IRQ */
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enable_interrupt(irq_id, CPU_0, 0);
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} else
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/* disable the IRQ */
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disable_interrupt(irq_id, CPU_0);
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}
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void uart_init(uint32_t instance, uint32_t baudrate, uint8_t parity,
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uint8_t stopbits, uint8_t datasize, uint8_t flowcontrol)
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{
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uint32_t base = REGS_UART_BASE(instance);
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/* configure the I/O for the port */
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uart_iomux_config(instance);
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/* enable the source clocks to the UART port */
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clock_gating_config(base, CLOCK_ON);
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/* Wait for UART to finish transmitting before changing the configuration */
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while (!(HW_UART_UTS(instance).B.TXEMPTY)) ;
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/* Disable UART */
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HW_UART_UCR1_CLR(instance,BM_UART_UCR1_UARTEN );
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/* Configure FIFOs trigger level to half-full and half-empty */
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HW_UART_UFCR_WR(instance, BF_UART_UFCR_RXTL(16) | UART_UFCR_RFDIV | BF_UART_UFCR_TXTL(16));
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/* Setup One Millisecond timer */
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HW_UART_ONEMS_WR(instance, uart_get_reffreq(instance) / 1000);
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/* Set parity */
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if (parity == PARITY_NONE)
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HW_UART_UCR2_CLR(instance,(BM_UART_UCR2_PREN| BM_UART_UCR2_PROE));
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else if (parity == PARITY_ODD)
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HW_UART_UCR2_SET(instance,(BM_UART_UCR2_PREN| BM_UART_UCR2_PROE));
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else { /* parity == PARITY_EVEN */
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HW_UART_UCR2_SET(instance, BM_UART_UCR2_PREN);
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HW_UART_UCR2_CLR(instance, BM_UART_UCR2_PROE);
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}
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/* Set stop bit */
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if (stopbits == STOPBITS_ONE)
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HW_UART_UCR2_CLR(instance, BM_UART_UCR2_STPB);
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else /* stopbits == STOPBITS_TWO */
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HW_UART_UCR2_SET(instance, BM_UART_UCR2_STPB);
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/* Set data size */
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if (datasize == EIGHTBITS)
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HW_UART_UCR2_SET(instance, BM_UART_UCR2_WS);
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else /* stopbits == STOPBITS_TWO */
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HW_UART_UCR2_CLR(instance, BM_UART_UCR2_WS);
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/* Configure the flow control */
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if (flowcontrol == FLOWCTRL_ON) {
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/* transmit done when RTS asserted */
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HW_UART_UCR2_CLR(instance, BM_UART_UCR2_IRTS );
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/* CTS controlled by the receiver */
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HW_UART_UCR2_SET(instance, BM_UART_UCR2_CTSC );
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} else { /* flowcontrol == FLOWCTRL_OFF */
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/* Ignore RTS */
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HW_UART_UCR2_SET(instance, BM_UART_UCR2_IRTS);
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/* CTS controlled by the CTS bit */
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HW_UART_UCR2_CLR(instance, BM_UART_UCR2_CTSC);
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}
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/* the reference manual says that this bit must always be set */
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HW_UART_UCR3_SET(instance, BM_UART_UCR3_RXDMUXSEL);
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/* Enable UART */
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HW_UART_UCR1_SET(instance, BM_UART_UCR1_UARTEN);
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/* Enable FIFOs and does software reset to clear status flags, reset
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the transmit and receive state machine, and reset the FIFOs */
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HW_UART_UCR2_SET(instance, BM_UART_UCR2_TXEN | BM_UART_UCR2_RXEN | BM_UART_UCR2_SRST);
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/* Set the numerator value minus one of the BRM ratio */
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HW_UART_UBIR_WR(instance, (baudrate / 100) - 1);
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/* Set the denominator value minus one of the BRM ratio */
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HW_UART_UBMR_WR(instance, ((uart_get_reffreq(instance) / 1600) - 1));
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/* Optional: prevent the UART to enter debug state. Useful when debugging
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the code with a JTAG and without active IRQ */
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HW_UART_UTS_SET(instance, BM_UART_UTS_DBGEN);
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}
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