549 lines
25 KiB
C
549 lines
25 KiB
C
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//*****************************************************************************
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//
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// hw_shamd5.h - Macros used when accessing the SHA/MD5 hardware.
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//
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// Copyright (c) 2012-2014 Texas Instruments Incorporated. All rights reserved.
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// Software License Agreement
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
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//
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//*****************************************************************************
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#ifndef __HW_SHAMD5_H__
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#define __HW_SHAMD5_H__
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//*****************************************************************************
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//
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// The following are defines for the SHA/MD5 register offsets.
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//
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//*****************************************************************************
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#define SHAMD5_O_ODIGEST_A 0x00000000 // SHA Outer Digest A
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#define SHAMD5_O_ODIGEST_B 0x00000004 // SHA Outer Digest B
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#define SHAMD5_O_ODIGEST_C 0x00000008 // SHA Outer Digest C
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#define SHAMD5_O_ODIGEST_D 0x0000000C // SHA Outer Digest D
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#define SHAMD5_O_ODIGEST_E 0x00000010 // SHA Outer Digest E
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#define SHAMD5_O_ODIGEST_F 0x00000014 // SHA Outer Digest F
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#define SHAMD5_O_ODIGEST_G 0x00000018 // SHA Outer Digest G
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#define SHAMD5_O_ODIGEST_H 0x0000001C // SHA Outer Digest H
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#define SHAMD5_O_IDIGEST_A 0x00000020 // SHA Inner Digest A
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#define SHAMD5_O_IDIGEST_B 0x00000024 // SHA Inner Digest B
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#define SHAMD5_O_IDIGEST_C 0x00000028 // SHA Inner Digest C
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#define SHAMD5_O_IDIGEST_D 0x0000002C // SHA Inner Digest D
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#define SHAMD5_O_IDIGEST_E 0x00000030 // SHA Inner Digest E
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#define SHAMD5_O_IDIGEST_F 0x00000034 // SHA Inner Digest F
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#define SHAMD5_O_IDIGEST_G 0x00000038 // SHA Inner Digest G
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#define SHAMD5_O_IDIGEST_H 0x0000003C // SHA Inner Digest H
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#define SHAMD5_O_DIGEST_COUNT 0x00000040 // SHA Digest Count
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#define SHAMD5_O_MODE 0x00000044 // SHA Mode
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#define SHAMD5_O_LENGTH 0x00000048 // SHA Length
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#define SHAMD5_O_DATA_0_IN 0x00000080 // SHA Data 0 Input
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#define SHAMD5_O_DATA_1_IN 0x00000084 // SHA Data 1 Input
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#define SHAMD5_O_DATA_2_IN 0x00000088 // SHA Data 2 Input
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#define SHAMD5_O_DATA_3_IN 0x0000008C // SHA Data 3 Input
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#define SHAMD5_O_DATA_4_IN 0x00000090 // SHA Data 4 Input
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#define SHAMD5_O_DATA_5_IN 0x00000094 // SHA Data 5 Input
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#define SHAMD5_O_DATA_6_IN 0x00000098 // SHA Data 6 Input
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#define SHAMD5_O_DATA_7_IN 0x0000009C // SHA Data 7 Input
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#define SHAMD5_O_DATA_8_IN 0x000000A0 // SHA Data 8 Input
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#define SHAMD5_O_DATA_9_IN 0x000000A4 // SHA Data 9 Input
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#define SHAMD5_O_DATA_10_IN 0x000000A8 // SHA Data 10 Input
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#define SHAMD5_O_DATA_11_IN 0x000000AC // SHA Data 11 Input
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#define SHAMD5_O_DATA_12_IN 0x000000B0 // SHA Data 12 Input
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#define SHAMD5_O_DATA_13_IN 0x000000B4 // SHA Data 13 Input
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#define SHAMD5_O_DATA_14_IN 0x000000B8 // SHA Data 14 Input
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#define SHAMD5_O_DATA_15_IN 0x000000BC // SHA Data 15 Input
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#define SHAMD5_O_REVISION 0x00000100 // SHA Revision
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#define SHAMD5_O_SYSCONFIG 0x00000110 // SHA System Configuration
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#define SHAMD5_O_SYSSTATUS 0x00000114 // SHA System Status
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#define SHAMD5_O_IRQSTATUS 0x00000118 // SHA Interrupt Status
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#define SHAMD5_O_IRQENABLE 0x0000011C // SHA Interrupt Enable
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#define SHAMD5_O_DMAIM 0xFFFFC010 // SHA DMA Interrupt Mask
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#define SHAMD5_O_DMARIS 0xFFFFC014 // SHA DMA Raw Interrupt Status
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#define SHAMD5_O_DMAMIS 0xFFFFC018 // SHA DMA Masked Interrupt Status
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#define SHAMD5_O_DMAIC 0xFFFFC01C // SHA DMA Interrupt Clear
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_A
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// register.
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//
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//*****************************************************************************
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#define SHAMD5_ODIGEST_A_DATA_M 0xFFFFFFFF // Digest/Key Data
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#define SHAMD5_ODIGEST_A_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_B
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// register.
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//
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//*****************************************************************************
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#define SHAMD5_ODIGEST_B_DATA_M 0xFFFFFFFF // Digest/Key Data
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#define SHAMD5_ODIGEST_B_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_C
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// register.
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//
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//*****************************************************************************
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#define SHAMD5_ODIGEST_C_DATA_M 0xFFFFFFFF // Digest/Key Data
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#define SHAMD5_ODIGEST_C_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_D
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// register.
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//
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//*****************************************************************************
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#define SHAMD5_ODIGEST_D_DATA_M 0xFFFFFFFF // Digest/Key Data
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#define SHAMD5_ODIGEST_D_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_E
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// register.
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//
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//*****************************************************************************
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#define SHAMD5_ODIGEST_E_DATA_M 0xFFFFFFFF // Digest/Key Data
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#define SHAMD5_ODIGEST_E_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_F
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// register.
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//
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//*****************************************************************************
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#define SHAMD5_ODIGEST_F_DATA_M 0xFFFFFFFF // Digest/Key Data
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#define SHAMD5_ODIGEST_F_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_G
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// register.
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//
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//*****************************************************************************
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#define SHAMD5_ODIGEST_G_DATA_M 0xFFFFFFFF // Digest/Key Data
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#define SHAMD5_ODIGEST_G_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_H
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// register.
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//
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//*****************************************************************************
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#define SHAMD5_ODIGEST_H_DATA_M 0xFFFFFFFF // Digest/Key Data
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#define SHAMD5_ODIGEST_H_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_A
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// register.
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//
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//*****************************************************************************
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#define SHAMD5_IDIGEST_A_DATA_M 0xFFFFFFFF // Digest/Key Data
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#define SHAMD5_IDIGEST_A_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_B
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// register.
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//
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//*****************************************************************************
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#define SHAMD5_IDIGEST_B_DATA_M 0xFFFFFFFF // Digest/Key Data
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#define SHAMD5_IDIGEST_B_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_C
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// register.
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//
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//*****************************************************************************
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#define SHAMD5_IDIGEST_C_DATA_M 0xFFFFFFFF // Digest/Key Data
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#define SHAMD5_IDIGEST_C_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_D
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// register.
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//
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//*****************************************************************************
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#define SHAMD5_IDIGEST_D_DATA_M 0xFFFFFFFF // Digest/Key Data
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#define SHAMD5_IDIGEST_D_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_E
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// register.
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//
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//*****************************************************************************
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#define SHAMD5_IDIGEST_E_DATA_M 0xFFFFFFFF // Digest/Key Data
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#define SHAMD5_IDIGEST_E_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_F
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// register.
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//
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//*****************************************************************************
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#define SHAMD5_IDIGEST_F_DATA_M 0xFFFFFFFF // Digest/Key Data
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#define SHAMD5_IDIGEST_F_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_G
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// register.
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//
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//*****************************************************************************
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#define SHAMD5_IDIGEST_G_DATA_M 0xFFFFFFFF // Digest/Key Data
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#define SHAMD5_IDIGEST_G_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_H
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// register.
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//
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//*****************************************************************************
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#define SHAMD5_IDIGEST_H_DATA_M 0xFFFFFFFF // Digest/Key Data
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#define SHAMD5_IDIGEST_H_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SHAMD5_O_DIGEST_COUNT
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// register.
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//
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//*****************************************************************************
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#define SHAMD5_DIGEST_COUNT_M 0xFFFFFFFF // Digest Count
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#define SHAMD5_DIGEST_COUNT_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SHAMD5_O_MODE register.
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//
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//*****************************************************************************
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#define SHAMD5_MODE_HMAC_OUTER_HASH \
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0x00000080 // HMAC Outer Hash Processing
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// Enable
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#define SHAMD5_MODE_HMAC_KEY_PROC \
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0x00000020 // HMAC Key Processing Enable
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#define SHAMD5_MODE_CLOSE_HASH 0x00000010 // Performs the padding, the
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// Hash/HMAC will be 'closed' at
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// the end of the block, as per
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// MD5/SHA-1/SHA-2 specification
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#define SHAMD5_MODE_ALGO_CONSTANT \
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0x00000008 // The initial digest register will
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// be overwritten with the
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// algorithm constants for the
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// selected algorithm when hashing
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// and the initial digest count
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// register will be reset to 0
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#define SHAMD5_MODE_ALGO_M 0x00000007 // Hash Algorithm
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#define SHAMD5_MODE_ALGO_MD5 0x00000000 // MD5
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#define SHAMD5_MODE_ALGO_SHA1 0x00000002 // SHA-1
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#define SHAMD5_MODE_ALGO_SHA224 0x00000004 // SHA-224
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#define SHAMD5_MODE_ALGO_SHA256 0x00000006 // SHA-256
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SHAMD5_O_LENGTH
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// register.
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//
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//*****************************************************************************
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#define SHAMD5_LENGTH_M 0xFFFFFFFF // Block Length/Remaining Byte
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// Count
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#define SHAMD5_LENGTH_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SHAMD5_O_DATA_0_IN
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// register.
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//
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//*****************************************************************************
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#define SHAMD5_DATA_0_IN_DATA_M 0xFFFFFFFF // Digest/Key Data
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#define SHAMD5_DATA_0_IN_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SHAMD5_O_DATA_1_IN
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// register.
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//
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//*****************************************************************************
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#define SHAMD5_DATA_1_IN_DATA_M 0xFFFFFFFF // Digest/Key Data
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#define SHAMD5_DATA_1_IN_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SHAMD5_O_DATA_2_IN
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// register.
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//
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//*****************************************************************************
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#define SHAMD5_DATA_2_IN_DATA_M 0xFFFFFFFF // Digest/Key Data
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#define SHAMD5_DATA_2_IN_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SHAMD5_O_DATA_3_IN
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// register.
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//
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//*****************************************************************************
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#define SHAMD5_DATA_3_IN_DATA_M 0xFFFFFFFF // Digest/Key Data
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#define SHAMD5_DATA_3_IN_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SHAMD5_O_DATA_4_IN
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// register.
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//
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//*****************************************************************************
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#define SHAMD5_DATA_4_IN_DATA_M 0xFFFFFFFF // Digest/Key Data
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#define SHAMD5_DATA_4_IN_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SHAMD5_O_DATA_5_IN
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// register.
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//
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//*****************************************************************************
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#define SHAMD5_DATA_5_IN_DATA_M 0xFFFFFFFF // Digest/Key Data
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#define SHAMD5_DATA_5_IN_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SHAMD5_O_DATA_6_IN
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// register.
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//
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//*****************************************************************************
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||
|
|
#define SHAMD5_DATA_6_IN_DATA_M 0xFFFFFFFF // Digest/Key Data
|
||
|
|
#define SHAMD5_DATA_6_IN_DATA_S 0
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the SHAMD5_O_DATA_7_IN
|
||
|
|
// register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define SHAMD5_DATA_7_IN_DATA_M 0xFFFFFFFF // Digest/Key Data
|
||
|
|
#define SHAMD5_DATA_7_IN_DATA_S 0
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the SHAMD5_O_DATA_8_IN
|
||
|
|
// register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define SHAMD5_DATA_8_IN_DATA_M 0xFFFFFFFF // Digest/Key Data
|
||
|
|
#define SHAMD5_DATA_8_IN_DATA_S 0
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the SHAMD5_O_DATA_9_IN
|
||
|
|
// register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define SHAMD5_DATA_9_IN_DATA_M 0xFFFFFFFF // Digest/Key Data
|
||
|
|
#define SHAMD5_DATA_9_IN_DATA_S 0
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the SHAMD5_O_DATA_10_IN
|
||
|
|
// register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define SHAMD5_DATA_10_IN_DATA_M \
|
||
|
|
0xFFFFFFFF // Digest/Key Data
|
||
|
|
#define SHAMD5_DATA_10_IN_DATA_S \
|
||
|
|
0
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the SHAMD5_O_DATA_11_IN
|
||
|
|
// register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define SHAMD5_DATA_11_IN_DATA_M \
|
||
|
|
0xFFFFFFFF // Digest/Key Data
|
||
|
|
#define SHAMD5_DATA_11_IN_DATA_S \
|
||
|
|
0
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the SHAMD5_O_DATA_12_IN
|
||
|
|
// register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define SHAMD5_DATA_12_IN_DATA_M \
|
||
|
|
0xFFFFFFFF // Digest/Key Data
|
||
|
|
#define SHAMD5_DATA_12_IN_DATA_S \
|
||
|
|
0
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the SHAMD5_O_DATA_13_IN
|
||
|
|
// register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define SHAMD5_DATA_13_IN_DATA_M \
|
||
|
|
0xFFFFFFFF // Digest/Key Data
|
||
|
|
#define SHAMD5_DATA_13_IN_DATA_S \
|
||
|
|
0
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the SHAMD5_O_DATA_14_IN
|
||
|
|
// register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define SHAMD5_DATA_14_IN_DATA_M \
|
||
|
|
0xFFFFFFFF // Digest/Key Data
|
||
|
|
#define SHAMD5_DATA_14_IN_DATA_S \
|
||
|
|
0
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the SHAMD5_O_DATA_15_IN
|
||
|
|
// register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define SHAMD5_DATA_15_IN_DATA_M \
|
||
|
|
0xFFFFFFFF // Digest/Key Data
|
||
|
|
#define SHAMD5_DATA_15_IN_DATA_S \
|
||
|
|
0
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the SHAMD5_O_REVISION
|
||
|
|
// register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define SHAMD5_REVISION_M 0xFFFFFFFF // Revision Number
|
||
|
|
#define SHAMD5_REVISION_S 0
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the SHAMD5_O_SYSCONFIG
|
||
|
|
// register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define SHAMD5_SYSCONFIG_SADVANCED \
|
||
|
|
0x00000080 // Advanced Mode Enable
|
||
|
|
#define SHAMD5_SYSCONFIG_SIDLE_M \
|
||
|
|
0x00000030 // Sidle mode
|
||
|
|
#define SHAMD5_SYSCONFIG_SIDLE_FORCE \
|
||
|
|
0x00000000 // Force-idle mode
|
||
|
|
#define SHAMD5_SYSCONFIG_DMA_EN 0x00000008 // uDMA Request Enable
|
||
|
|
#define SHAMD5_SYSCONFIG_IT_EN 0x00000004 // Interrupt Enable
|
||
|
|
#define SHAMD5_SYSCONFIG_SOFTRESET \
|
||
|
|
0x00000002 // Soft reset
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the SHAMD5_O_SYSSTATUS
|
||
|
|
// register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define SHAMD5_SYSSTATUS_RESETDONE \
|
||
|
|
0x00000001 // Reset done status
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the SHAMD5_O_IRQSTATUS
|
||
|
|
// register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define SHAMD5_IRQSTATUS_CONTEXT_READY \
|
||
|
|
0x00000008 // Context Ready Status
|
||
|
|
#define SHAMD5_IRQSTATUS_INPUT_READY \
|
||
|
|
0x00000002 // Input Ready Status
|
||
|
|
#define SHAMD5_IRQSTATUS_OUTPUT_READY \
|
||
|
|
0x00000001 // Output Ready Status
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the SHAMD5_O_IRQENABLE
|
||
|
|
// register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define SHAMD5_IRQENABLE_CONTEXT_READY \
|
||
|
|
0x00000008 // Mask for context ready interrupt
|
||
|
|
#define SHAMD5_IRQENABLE_INPUT_READY \
|
||
|
|
0x00000002 // Mask for input ready interrupt
|
||
|
|
#define SHAMD5_IRQENABLE_OUTPUT_READY \
|
||
|
|
0x00000001 // Mask for output ready interrupt
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the SHAMD5_O_DMAIM register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define SHAMD5_DMAIM_COUT 0x00000004 // Context Out DMA Done Interrupt
|
||
|
|
// Mask
|
||
|
|
#define SHAMD5_DMAIM_DIN 0x00000002 // Data In DMA Done Interrupt Mask
|
||
|
|
#define SHAMD5_DMAIM_CIN 0x00000001 // Context In DMA Done Interrupt
|
||
|
|
// Mask
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the SHAMD5_O_DMARIS
|
||
|
|
// register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define SHAMD5_DMARIS_COUT 0x00000004 // Context Out DMA Done Raw
|
||
|
|
// Interrupt Status
|
||
|
|
#define SHAMD5_DMARIS_DIN 0x00000002 // Data In DMA Done Raw Interrupt
|
||
|
|
// Status
|
||
|
|
#define SHAMD5_DMARIS_CIN 0x00000001 // Context In DMA Done Raw
|
||
|
|
// Interrupt Status
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the SHAMD5_O_DMAMIS
|
||
|
|
// register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define SHAMD5_DMAMIS_COUT 0x00000004 // Context Out DMA Done Masked
|
||
|
|
// Interrupt Status
|
||
|
|
#define SHAMD5_DMAMIS_DIN 0x00000002 // Data In DMA Done Masked
|
||
|
|
// Interrupt Status
|
||
|
|
#define SHAMD5_DMAMIS_CIN 0x00000001 // Context In DMA Done Raw
|
||
|
|
// Interrupt Status
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the SHAMD5_O_DMAIC register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define SHAMD5_DMAIC_COUT 0x00000004 // Context Out DMA Done Masked
|
||
|
|
// Interrupt Status
|
||
|
|
#define SHAMD5_DMAIC_DIN 0x00000002 // Data In DMA Done Interrupt Clear
|
||
|
|
#define SHAMD5_DMAIC_CIN 0x00000001 // Context In DMA Done Raw
|
||
|
|
// Interrupt Status
|
||
|
|
|
||
|
|
#endif // __HW_SHAMD5_H__
|