463 lines
22 KiB
C
463 lines
22 KiB
C
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//*****************************************************************************
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//
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// hw_can.h - Defines and macros used when accessing the CAN controllers.
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//
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// Copyright (c) 2006-2014 Texas Instruments Incorporated. All rights reserved.
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// Software License Agreement
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
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//
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//*****************************************************************************
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#ifndef __HW_CAN_H__
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#define __HW_CAN_H__
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//*****************************************************************************
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//
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// The following are defines for the CAN register offsets.
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//
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//*****************************************************************************
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#define CAN_O_CTL 0x00000000 // CAN Control
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#define CAN_O_STS 0x00000004 // CAN Status
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#define CAN_O_ERR 0x00000008 // CAN Error Counter
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#define CAN_O_BIT 0x0000000C // CAN Bit Timing
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#define CAN_O_INT 0x00000010 // CAN Interrupt
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#define CAN_O_TST 0x00000014 // CAN Test
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#define CAN_O_BRPE 0x00000018 // CAN Baud Rate Prescaler
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// Extension
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#define CAN_O_IF1CRQ 0x00000020 // CAN IF1 Command Request
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#define CAN_O_IF1CMSK 0x00000024 // CAN IF1 Command Mask
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#define CAN_O_IF1MSK1 0x00000028 // CAN IF1 Mask 1
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#define CAN_O_IF1MSK2 0x0000002C // CAN IF1 Mask 2
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#define CAN_O_IF1ARB1 0x00000030 // CAN IF1 Arbitration 1
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#define CAN_O_IF1ARB2 0x00000034 // CAN IF1 Arbitration 2
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#define CAN_O_IF1MCTL 0x00000038 // CAN IF1 Message Control
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#define CAN_O_IF1DA1 0x0000003C // CAN IF1 Data A1
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#define CAN_O_IF1DA2 0x00000040 // CAN IF1 Data A2
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#define CAN_O_IF1DB1 0x00000044 // CAN IF1 Data B1
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#define CAN_O_IF1DB2 0x00000048 // CAN IF1 Data B2
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#define CAN_O_IF2CRQ 0x00000080 // CAN IF2 Command Request
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#define CAN_O_IF2CMSK 0x00000084 // CAN IF2 Command Mask
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#define CAN_O_IF2MSK1 0x00000088 // CAN IF2 Mask 1
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#define CAN_O_IF2MSK2 0x0000008C // CAN IF2 Mask 2
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#define CAN_O_IF2ARB1 0x00000090 // CAN IF2 Arbitration 1
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#define CAN_O_IF2ARB2 0x00000094 // CAN IF2 Arbitration 2
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#define CAN_O_IF2MCTL 0x00000098 // CAN IF2 Message Control
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#define CAN_O_IF2DA1 0x0000009C // CAN IF2 Data A1
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#define CAN_O_IF2DA2 0x000000A0 // CAN IF2 Data A2
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#define CAN_O_IF2DB1 0x000000A4 // CAN IF2 Data B1
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#define CAN_O_IF2DB2 0x000000A8 // CAN IF2 Data B2
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#define CAN_O_TXRQ1 0x00000100 // CAN Transmission Request 1
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#define CAN_O_TXRQ2 0x00000104 // CAN Transmission Request 2
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#define CAN_O_NWDA1 0x00000120 // CAN New Data 1
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#define CAN_O_NWDA2 0x00000124 // CAN New Data 2
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#define CAN_O_MSG1INT 0x00000140 // CAN Message 1 Interrupt Pending
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#define CAN_O_MSG2INT 0x00000144 // CAN Message 2 Interrupt Pending
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#define CAN_O_MSG1VAL 0x00000160 // CAN Message 1 Valid
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#define CAN_O_MSG2VAL 0x00000164 // CAN Message 2 Valid
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the CAN_O_CTL register.
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//
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//*****************************************************************************
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#define CAN_CTL_TEST 0x00000080 // Test Mode Enable
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#define CAN_CTL_CCE 0x00000040 // Configuration Change Enable
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#define CAN_CTL_DAR 0x00000020 // Disable Automatic-Retransmission
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#define CAN_CTL_EIE 0x00000008 // Error Interrupt Enable
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#define CAN_CTL_SIE 0x00000004 // Status Interrupt Enable
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#define CAN_CTL_IE 0x00000002 // CAN Interrupt Enable
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#define CAN_CTL_INIT 0x00000001 // Initialization
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the CAN_O_STS register.
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//
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//*****************************************************************************
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#define CAN_STS_BOFF 0x00000080 // Bus-Off Status
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#define CAN_STS_EWARN 0x00000040 // Warning Status
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#define CAN_STS_EPASS 0x00000020 // Error Passive
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#define CAN_STS_RXOK 0x00000010 // Received a Message Successfully
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#define CAN_STS_TXOK 0x00000008 // Transmitted a Message
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// Successfully
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#define CAN_STS_LEC_M 0x00000007 // Last Error Code
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#define CAN_STS_LEC_NONE 0x00000000 // No Error
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#define CAN_STS_LEC_STUFF 0x00000001 // Stuff Error
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#define CAN_STS_LEC_FORM 0x00000002 // Format Error
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#define CAN_STS_LEC_ACK 0x00000003 // ACK Error
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#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 Error
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#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 Error
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#define CAN_STS_LEC_CRC 0x00000006 // CRC Error
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#define CAN_STS_LEC_NOEVENT 0x00000007 // No Event
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the CAN_O_ERR register.
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//
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//*****************************************************************************
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#define CAN_ERR_RP 0x00008000 // Received Error Passive
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#define CAN_ERR_REC_M 0x00007F00 // Receive Error Counter
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#define CAN_ERR_TEC_M 0x000000FF // Transmit Error Counter
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#define CAN_ERR_REC_S 8
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#define CAN_ERR_TEC_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the CAN_O_BIT register.
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//
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//*****************************************************************************
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#define CAN_BIT_TSEG2_M 0x00007000 // Time Segment after Sample Point
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#define CAN_BIT_TSEG1_M 0x00000F00 // Time Segment Before Sample Point
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#define CAN_BIT_SJW_M 0x000000C0 // (Re)Synchronization Jump Width
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#define CAN_BIT_BRP_M 0x0000003F // Baud Rate Prescaler
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#define CAN_BIT_TSEG2_S 12
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#define CAN_BIT_TSEG1_S 8
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#define CAN_BIT_SJW_S 6
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#define CAN_BIT_BRP_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the CAN_O_INT register.
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//
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//*****************************************************************************
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#define CAN_INT_INTID_M 0x0000FFFF // Interrupt Identifier
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#define CAN_INT_INTID_NONE 0x00000000 // No interrupt pending
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#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the CAN_O_TST register.
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//
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//*****************************************************************************
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#define CAN_TST_RX 0x00000080 // Receive Observation
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#define CAN_TST_TX_M 0x00000060 // Transmit Control
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#define CAN_TST_TX_CANCTL 0x00000000 // CAN Module Control
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#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point
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#define CAN_TST_TX_DOMINANT 0x00000040 // Driven Low
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#define CAN_TST_TX_RECESSIVE 0x00000060 // Driven High
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#define CAN_TST_LBACK 0x00000010 // Loopback Mode
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#define CAN_TST_SILENT 0x00000008 // Silent Mode
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#define CAN_TST_BASIC 0x00000004 // Basic Mode
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the CAN_O_BRPE register.
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//
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//*****************************************************************************
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#define CAN_BRPE_BRPE_M 0x0000000F // Baud Rate Prescaler Extension
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#define CAN_BRPE_BRPE_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the CAN_O_IF1CRQ register.
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//
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//*****************************************************************************
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#define CAN_IF1CRQ_BUSY 0x00008000 // Busy Flag
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#define CAN_IF1CRQ_MNUM_M 0x0000003F // Message Number
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#define CAN_IF1CRQ_MNUM_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the CAN_O_IF1CMSK register.
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//
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//*****************************************************************************
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#define CAN_IF1CMSK_WRNRD 0x00000080 // Write, Not Read
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#define CAN_IF1CMSK_MASK 0x00000040 // Access Mask Bits
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#define CAN_IF1CMSK_ARB 0x00000020 // Access Arbitration Bits
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#define CAN_IF1CMSK_CONTROL 0x00000010 // Access Control Bits
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#define CAN_IF1CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit
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#define CAN_IF1CMSK_NEWDAT 0x00000004 // Access New Data
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#define CAN_IF1CMSK_TXRQST 0x00000004 // Access Transmission Request
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#define CAN_IF1CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3
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#define CAN_IF1CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the CAN_O_IF1MSK1 register.
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//
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//*****************************************************************************
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#define CAN_IF1MSK1_IDMSK_M 0x0000FFFF // Identifier Mask
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#define CAN_IF1MSK1_IDMSK_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the CAN_O_IF1MSK2 register.
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//
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//*****************************************************************************
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#define CAN_IF1MSK2_MXTD 0x00008000 // Mask Extended Identifier
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#define CAN_IF1MSK2_MDIR 0x00004000 // Mask Message Direction
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#define CAN_IF1MSK2_IDMSK_M 0x00001FFF // Identifier Mask
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#define CAN_IF1MSK2_IDMSK_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the CAN_O_IF1ARB1 register.
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//
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//*****************************************************************************
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#define CAN_IF1ARB1_ID_M 0x0000FFFF // Message Identifier
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#define CAN_IF1ARB1_ID_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the CAN_O_IF1ARB2 register.
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//
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//*****************************************************************************
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#define CAN_IF1ARB2_MSGVAL 0x00008000 // Message Valid
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#define CAN_IF1ARB2_XTD 0x00004000 // Extended Identifier
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#define CAN_IF1ARB2_DIR 0x00002000 // Message Direction
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#define CAN_IF1ARB2_ID_M 0x00001FFF // Message Identifier
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#define CAN_IF1ARB2_ID_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the CAN_O_IF1MCTL register.
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//
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//*****************************************************************************
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#define CAN_IF1MCTL_NEWDAT 0x00008000 // New Data
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#define CAN_IF1MCTL_MSGLST 0x00004000 // Message Lost
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#define CAN_IF1MCTL_INTPND 0x00002000 // Interrupt Pending
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#define CAN_IF1MCTL_UMASK 0x00001000 // Use Acceptance Mask
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#define CAN_IF1MCTL_TXIE 0x00000800 // Transmit Interrupt Enable
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#define CAN_IF1MCTL_RXIE 0x00000400 // Receive Interrupt Enable
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#define CAN_IF1MCTL_RMTEN 0x00000200 // Remote Enable
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#define CAN_IF1MCTL_TXRQST 0x00000100 // Transmit Request
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#define CAN_IF1MCTL_EOB 0x00000080 // End of Buffer
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#define CAN_IF1MCTL_DLC_M 0x0000000F // Data Length Code
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#define CAN_IF1MCTL_DLC_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the CAN_O_IF1DA1 register.
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//
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//*****************************************************************************
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#define CAN_IF1DA1_DATA_M 0x0000FFFF // Data
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#define CAN_IF1DA1_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the CAN_O_IF1DA2 register.
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//
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//*****************************************************************************
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#define CAN_IF1DA2_DATA_M 0x0000FFFF // Data
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#define CAN_IF1DA2_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the CAN_O_IF1DB1 register.
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//
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//*****************************************************************************
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#define CAN_IF1DB1_DATA_M 0x0000FFFF // Data
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#define CAN_IF1DB1_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the CAN_O_IF1DB2 register.
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//
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//*****************************************************************************
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#define CAN_IF1DB2_DATA_M 0x0000FFFF // Data
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#define CAN_IF1DB2_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the CAN_O_IF2CRQ register.
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//
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//*****************************************************************************
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#define CAN_IF2CRQ_BUSY 0x00008000 // Busy Flag
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#define CAN_IF2CRQ_MNUM_M 0x0000003F // Message Number
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#define CAN_IF2CRQ_MNUM_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the CAN_O_IF2CMSK register.
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//
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//*****************************************************************************
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#define CAN_IF2CMSK_WRNRD 0x00000080 // Write, Not Read
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#define CAN_IF2CMSK_MASK 0x00000040 // Access Mask Bits
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#define CAN_IF2CMSK_ARB 0x00000020 // Access Arbitration Bits
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#define CAN_IF2CMSK_CONTROL 0x00000010 // Access Control Bits
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#define CAN_IF2CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit
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#define CAN_IF2CMSK_NEWDAT 0x00000004 // Access New Data
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#define CAN_IF2CMSK_TXRQST 0x00000004 // Access Transmission Request
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#define CAN_IF2CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3
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#define CAN_IF2CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the CAN_O_IF2MSK1 register.
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//
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//*****************************************************************************
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#define CAN_IF2MSK1_IDMSK_M 0x0000FFFF // Identifier Mask
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#define CAN_IF2MSK1_IDMSK_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the CAN_O_IF2MSK2 register.
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//
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//*****************************************************************************
|
||
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#define CAN_IF2MSK2_MXTD 0x00008000 // Mask Extended Identifier
|
||
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#define CAN_IF2MSK2_MDIR 0x00004000 // Mask Message Direction
|
||
|
|
#define CAN_IF2MSK2_IDMSK_M 0x00001FFF // Identifier Mask
|
||
|
|
#define CAN_IF2MSK2_IDMSK_S 0
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||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
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// The following are defines for the bit fields in the CAN_O_IF2ARB1 register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
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||
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#define CAN_IF2ARB1_ID_M 0x0000FFFF // Message Identifier
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||
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#define CAN_IF2ARB1_ID_S 0
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||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
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// The following are defines for the bit fields in the CAN_O_IF2ARB2 register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
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||
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|
#define CAN_IF2ARB2_MSGVAL 0x00008000 // Message Valid
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||
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#define CAN_IF2ARB2_XTD 0x00004000 // Extended Identifier
|
||
|
|
#define CAN_IF2ARB2_DIR 0x00002000 // Message Direction
|
||
|
|
#define CAN_IF2ARB2_ID_M 0x00001FFF // Message Identifier
|
||
|
|
#define CAN_IF2ARB2_ID_S 0
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the CAN_O_IF2MCTL register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define CAN_IF2MCTL_NEWDAT 0x00008000 // New Data
|
||
|
|
#define CAN_IF2MCTL_MSGLST 0x00004000 // Message Lost
|
||
|
|
#define CAN_IF2MCTL_INTPND 0x00002000 // Interrupt Pending
|
||
|
|
#define CAN_IF2MCTL_UMASK 0x00001000 // Use Acceptance Mask
|
||
|
|
#define CAN_IF2MCTL_TXIE 0x00000800 // Transmit Interrupt Enable
|
||
|
|
#define CAN_IF2MCTL_RXIE 0x00000400 // Receive Interrupt Enable
|
||
|
|
#define CAN_IF2MCTL_RMTEN 0x00000200 // Remote Enable
|
||
|
|
#define CAN_IF2MCTL_TXRQST 0x00000100 // Transmit Request
|
||
|
|
#define CAN_IF2MCTL_EOB 0x00000080 // End of Buffer
|
||
|
|
#define CAN_IF2MCTL_DLC_M 0x0000000F // Data Length Code
|
||
|
|
#define CAN_IF2MCTL_DLC_S 0
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the CAN_O_IF2DA1 register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define CAN_IF2DA1_DATA_M 0x0000FFFF // Data
|
||
|
|
#define CAN_IF2DA1_DATA_S 0
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the CAN_O_IF2DA2 register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define CAN_IF2DA2_DATA_M 0x0000FFFF // Data
|
||
|
|
#define CAN_IF2DA2_DATA_S 0
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the CAN_O_IF2DB1 register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define CAN_IF2DB1_DATA_M 0x0000FFFF // Data
|
||
|
|
#define CAN_IF2DB1_DATA_S 0
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the CAN_O_IF2DB2 register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define CAN_IF2DB2_DATA_M 0x0000FFFF // Data
|
||
|
|
#define CAN_IF2DB2_DATA_S 0
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the CAN_O_TXRQ1 register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define CAN_TXRQ1_TXRQST_M 0x0000FFFF // Transmission Request Bits
|
||
|
|
#define CAN_TXRQ1_TXRQST_S 0
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the CAN_O_TXRQ2 register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define CAN_TXRQ2_TXRQST_M 0x0000FFFF // Transmission Request Bits
|
||
|
|
#define CAN_TXRQ2_TXRQST_S 0
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the CAN_O_NWDA1 register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define CAN_NWDA1_NEWDAT_M 0x0000FFFF // New Data Bits
|
||
|
|
#define CAN_NWDA1_NEWDAT_S 0
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the CAN_O_NWDA2 register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define CAN_NWDA2_NEWDAT_M 0x0000FFFF // New Data Bits
|
||
|
|
#define CAN_NWDA2_NEWDAT_S 0
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the CAN_O_MSG1INT register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define CAN_MSG1INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits
|
||
|
|
#define CAN_MSG1INT_INTPND_S 0
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the CAN_O_MSG2INT register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define CAN_MSG2INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits
|
||
|
|
#define CAN_MSG2INT_INTPND_S 0
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the CAN_O_MSG1VAL register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits
|
||
|
|
#define CAN_MSG1VAL_MSGVAL_S 0
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the CAN_O_MSG2VAL register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits
|
||
|
|
#define CAN_MSG2VAL_MSGVAL_S 0
|
||
|
|
|
||
|
|
#endif // __HW_CAN_H__
|