339 lines
14 KiB
ArmAsm
339 lines
14 KiB
ArmAsm
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;/*
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; * @brief LPC5410x M0 core startup code for Keil
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; *
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; * @note
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; * Copyright(C) NXP Semiconductors, 2014
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; * All rights reserved.
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; *
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; * @par
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; * Software that is described herein is for illustrative purposes only
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; * which provides customers with programming information regarding the
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; * LPC products. This software is supplied "AS IS" without any warranties of
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; * any kind, and NXP Semiconductors and its licensor disclaim any and
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; * all warranties, express or implied, including all implied warranties of
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; * merchantability, fitness for a particular purpose and non-infringement of
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; * intellectual property rights. NXP Semiconductors assumes no responsibility
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; * or liability for the use of the software, conveys no license or rights under any
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; * patent, copyright, mask work right, or any other intellectual property rights in
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; * or to any products. NXP Semiconductors reserves the right to make changes
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; * in the software without notification. NXP Semiconductors also makes no
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; * representation or warranty that such application will be suitable for the
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; * specified use without further testing or modification.
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; *
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; * @par
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; * Permission to use, copy, modify, and distribute this software and its
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; * documentation is hereby granted, under NXP Semiconductors' and its
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; * licensor's relevant copyrights in the software, without fee, provided that it
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; * is used in conjunction with NXP Semiconductors microcontrollers. This
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; * copyright, permission, and disclaimer notice must appear in all copies of
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; * this code.
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; */
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; <h> Stack Configuration
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; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Stack_Size EQU 0x00000200
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE Stack_Size
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__initial_sp
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; <h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Heap_Size EQU 0x00000000
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD 0
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DCD 0
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DCD 0
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__vector_table_0x1c
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DCD 0 ; Checksum of the first 7 words
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DCD 0
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DCD 0 ; Enhanced image marker, set to 0x0 for legacy boot
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DCD 0 ; Pointer to enhanced boot block, set to 0x0 for legacy boot
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DCD SVC_Handler ; SVCall Handler
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DCD 0
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DCD 0
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD WDT_IRQHandler ; Watchdog
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DCD BOD_IRQHandler ; Brown Out Detect
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DCD Reserved_IRQHandler ; Reserved
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DCD DMA_IRQHandler ; DMA Controller
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DCD GINT0_IRQHandler ; GPIO Group0 Interrupt
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DCD PIN_INT0_IRQHandler ; PIO INT0
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DCD PIN_INT1_IRQHandler ; PIO INT1
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DCD PIN_INT2_IRQHandler ; PIO INT2
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DCD PIN_INT3_IRQHandler ; PIO INT3
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DCD UTICK_IRQHandler ; UTICK timer
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DCD MRT_IRQHandler ; Multi-Rate Timer
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DCD CT32B0_IRQHandler ; CT32B0
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DCD CT32B1_IRQHandler ; CT32B1
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DCD CT32B2_IRQHandler ; CT32B2
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DCD CT32B3_IRQHandler ; CT32B3
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DCD CT32B4_IRQHandler ; CT32B4
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DCD SCT0_IRQHandler ; Smart Counter Timer
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DCD UART0_IRQHandler ; UART0
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DCD UART1_IRQHandler ; UART1
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DCD UART2_IRQHandler ; UART2
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DCD UART3_IRQHandler ; UART3
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DCD I2C0_IRQHandler ; I2C0 controller
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DCD I2C1_IRQHandler ; I2C1 controller
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DCD I2C2_IRQHandler ; I2C2 controller
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DCD SPI0_IRQHandler ; SPI0 controller
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DCD SPI1_IRQHandler ; SPI1 controller
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DCD ADC_SEQA_IRQHandler ; ADC0 A sequence (A/D Converter) interrupt
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DCD ADC_SEQB_IRQHandler ; ADC0 B sequence (A/D Converter) interrupt
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DCD ADC_THCMP_IRQHandler ; ADC THCMP and OVERRUN ORed
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DCD RTC_IRQHandler ; RTC Timer
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DCD Reserved_IRQHandler ; Reserved
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DCD MAILBOX_IRQHandler ; Mailbox
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;// <h> Code Read Protection level (CRP)
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;// <o> CRP_Level:
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;// <0xFFFFFFFF=> Disabled
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;// <0x4E697370=> NO_ISP
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;// <0x12345678=> CRP1
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;// <0x87654321=> CRP2
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;// <0x43218765=> CRP3 (Are you sure?)
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;// </h>
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CRP_Level EQU 0xFFFFFFFF
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IF :LNOT::DEF:NO_CRP
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AREA |.ARM.__at_0x02FC|, CODE, READONLY
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CRP_Key DCD 0xFFFFFFFF
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ENDIF
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AREA |.text|, CODE, READONLY
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cpu_id EQU 0xE000ED00
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cpu_ctrl EQU 0x40000300
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coproc_boot EQU 0x40000304
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coproc_stack EQU 0x40000308
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rel_vals
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DCD cpu_id, cpu_ctrl, coproc_boot, coproc_stack
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DCW 0xFFF, 0xC24
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; Reset Handler - shared for both cores
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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EXPORT SystemInit [WEAK]
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IMPORT __main
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IF :LNOT::DEF:SLAVEBOOT
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; Both the M0+ and M4 core come via this shared startup code,
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; but the M0+ and M4 core have different vector tables.
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; Determine if the core executing this code is the master or
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; the slave and handle each core state individually.
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shared_boot_entry
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LDR r6, =rel_vals
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MOVS r4, #0 ; Flag for slave core (0)
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MOVS r5, #1
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; Determine which core (M0+ or M4) this code is running on
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; r2 = (((*cpu_id) >> 4) & 0xFFF); (M4 core == 0xC24)
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get_current_core_id
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LDR r0, [r6, #0]
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LDR r1, [r0] ; r1 = CPU ID status
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LSRS r1, r1, #4 ; Right justify 12 CPU ID bits
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LDRH r2, [r6, #16] ; Mask for CPU ID bits
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ANDS r2, r1, r2 ; r2 = ARM COrtex CPU ID
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LDRH r3, [r6, #18] ; Mask for CPU ID bits
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CMP r3, r2 ; Core ID matches M4 identifier
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BNE get_master_status
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MOV r4, r5 ; Set flag for master core (1)
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; Determine if M4 core is the master or slave
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; r3 = ((*cpu_ctrl) & 1); (0 == m0+, 1 == M4)
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get_master_status
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LDR r0, [r6, #4]
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LDR r3, [r0] ; r3 = SYSCON co-processor CPU control status
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ANDS r3, r3, r5 ; r3 = (Bit 0: 1 = M4 is master, 0 = M4 is slave)
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; Select boot based on selected master core and core ID
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select_boot
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EORS r3, r3, r4 ; r4 = (Bit 0: 0 = master, 1 = slave)
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BNE slave_boot
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B normal_boot
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; Slave boot
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slave_boot
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LDR r0, [r6, #8]
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LDR r2, [r0] ; r1 = SYSCON co-processor boot address
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CMP r2, #0 ; Slave boot address = 0 (not set up)?
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BEQ cpu_sleep
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LDR r0, [r6, #12]
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LDR r1, [r0] ; r5 = SYSCON co-processor stack address
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MOV sp, r1 ; Update slave CPU stack pointer
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; Be sure to update VTOR for the slave MCU to point to the
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; slave vector table in boot memory
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BX r2 ; Jump to slave boot address
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; Slave isn't yet setup for system boot from the master
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; so sleep until the master sets it up and then reboots it
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cpu_sleep
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MOV sp, r5 ; Will force exception if something happens
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cpu_sleep_wfi
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WFI ; Sleep forever until master reboots
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B cpu_sleep_wfi
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ENDIF
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; Normal boot for master/slave
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normal_boot
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LDR r0, =SystemInit
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BLX r0
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LDR r0, =__main
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BX r0
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ENDP
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; For cores with SystemInit() or __main(), the code will sleep the MCU
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SystemInit PROC
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EXPORT SystemInit [WEAK]
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BX lr
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT WDT_IRQHandler [WEAK] ; Watchdog
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EXPORT BOD_IRQHandler [WEAK] ; Brown Out Detect
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EXPORT DMA_IRQHandler [WEAK] ; DMA Controller
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EXPORT GINT0_IRQHandler [WEAK] ; GPIO Group0 Interrupt
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EXPORT PIN_INT0_IRQHandler [WEAK] ; PIO INT0
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EXPORT PIN_INT1_IRQHandler [WEAK] ; PIO INT1
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EXPORT PIN_INT2_IRQHandler [WEAK] ; PIO INT2
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EXPORT PIN_INT3_IRQHandler [WEAK] ; PIO INT3
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EXPORT UTICK_IRQHandler [WEAK] ; UTICK timer
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EXPORT MRT_IRQHandler [WEAK] ; Multi-Rate Timer
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EXPORT CT32B0_IRQHandler [WEAK] ; CT32B0
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EXPORT CT32B1_IRQHandler [WEAK] ; CT32B1
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EXPORT CT32B2_IRQHandler [WEAK] ; CT32B2
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EXPORT CT32B3_IRQHandler [WEAK] ; CT32B3
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EXPORT CT32B4_IRQHandler [WEAK] ; CT32B4
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EXPORT UART0_IRQHandler [WEAK] ; UART0
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EXPORT SCT0_IRQHandler [WEAK] ; Smart Counter Timer
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EXPORT UART1_IRQHandler [WEAK] ; UART1
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EXPORT UART2_IRQHandler [WEAK] ; UART2
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EXPORT UART3_IRQHandler [WEAK] ; UART3
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EXPORT I2C0_IRQHandler [WEAK] ; I2C0 controller
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EXPORT I2C1_IRQHandler [WEAK] ; I2C1 controller
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EXPORT I2C2_IRQHandler [WEAK] ; I2C2 controller
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EXPORT SPI0_IRQHandler [WEAK] ; SPI0 controller
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EXPORT SPI1_IRQHandler [WEAK] ; SPI1 controller
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EXPORT ADC_SEQA_IRQHandler [WEAK] ; ADC0 A sequence (A/D Converter) interrupt
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EXPORT ADC_SEQB_IRQHandler [WEAK] ; ADC0 B sequence (A/D Converter) interrupt
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EXPORT ADC_THCMP_IRQHandler [WEAK] ; ADC THCMP and OVERRUN ORed
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EXPORT RTC_IRQHandler [WEAK] ; RTC Timer
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EXPORT MAILBOX_IRQHandler [WEAK] ; Mailbox
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EXPORT Reserved_IRQHandler [WEAK] ; Reserved
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WDT_IRQHandler ; Watchdog
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BOD_IRQHandler ; Brown Out Detect
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DMA_IRQHandler ; DMA Controller
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GINT0_IRQHandler ; GPIO Group0 Interrupt
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PIN_INT0_IRQHandler ; PIO INT0
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PIN_INT1_IRQHandler ; PIO INT1
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PIN_INT2_IRQHandler ; PIO INT2
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PIN_INT3_IRQHandler ; PIO INT3
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UTICK_IRQHandler ; UTICK timer
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MRT_IRQHandler ; Multi-Rate Timer
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CT32B0_IRQHandler ; CT32B0
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CT32B1_IRQHandler ; CT32B1
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CT32B2_IRQHandler ; CT32B2
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CT32B3_IRQHandler ; CT32B3
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CT32B4_IRQHandler ; CT32B4
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UART0_IRQHandler ; UART0
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SCT0_IRQHandler ; Smart Counter Timer
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UART1_IRQHandler ; UART1
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UART2_IRQHandler ; UART2
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UART3_IRQHandler ; UART3
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I2C0_IRQHandler ; I2C0 controller
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I2C1_IRQHandler ; I2C1 controller
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I2C2_IRQHandler ; I2C2 controller
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SPI0_IRQHandler ; SPI0 controller
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SPI1_IRQHandler ; SPI1 controller
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ADC_SEQA_IRQHandler ; ADC0 A sequence (A/D Converter) interrupt
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ADC_SEQB_IRQHandler ; ADC0 B sequence (A/D Converter) interrupt
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ADC_THCMP_IRQHandler ; ADC THCMP and OVERRUN ORed
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RTC_IRQHandler ; RTC Timer
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MAILBOX_IRQHandler ; Mailbox
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Reserved_IRQHandler ; Reserved
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B .
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ENDP
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ALIGN
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; User Initial Stack & Heap
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IF :DEF:__MICROLIB
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EXPORT __initial_sp
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EXPORT __heap_base
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EXPORT __heap_limit
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ELSE
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IMPORT __use_two_region_memory
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EXPORT __user_initial_stackheap
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__user_initial_stackheap
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LDR R0, = Heap_Mem
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LDR R1, =(Stack_Mem + Stack_Size)
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LDR R2, = (Heap_Mem + Heap_Size)
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LDR R3, = Stack_Mem
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BX LR
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ALIGN
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ENDIF
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END
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