149 lines
5.5 KiB
C
149 lines
5.5 KiB
C
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/*
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* This file is part of FH8620 BSP for RT-Thread distribution.
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*
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* Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
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* All rights reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Visit http://www.fullhan.com to get contact with Fullhan.
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*
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* Change Logs:
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* Date Author Notes
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*/
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#ifndef FH_SPI_H_
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#define FH_SPI_H_
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#include "fh_def.h"
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#include "fh_arch.h"
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#define OFFSET_SPI_CTRL0 (0x00)
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#define OFFSET_SPI_CTRL1 (0x04)
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#define OFFSET_SPI_SSIENR (0x08)
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#define OFFSET_SPI_MWCR (0x0c)
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#define OFFSET_SPI_SER (0x10)
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#define OFFSET_SPI_BAUD (0x14)
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#define OFFSET_SPI_TXFTLR (0x18)
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#define OFFSET_SPI_RXFTLR (0x1c)
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#define OFFSET_SPI_TXFLR (0x20)
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#define OFFSET_SPI_RXFLR (0x24)
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#define OFFSET_SPI_SR (0x28)
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#define OFFSET_SPI_IMR (0x2c)
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#define OFFSET_SPI_ISR (0x30)
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#define OFFSET_SPI_RISR (0x34)
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#define OFFSET_SPI_TXOIC (0x38)
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#define OFFSET_SPI_RXOIC (0x3c)
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#define OFFSET_SPI_RXUIC (0x40)
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#define OFFSET_SPI_MSTIC (0x44)
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#define OFFSET_SPI_ICR (0x48)
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#define OFFSET_SPI_DMACTRL (0x4c)
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#define OFFSET_SPI_DMATDL (0x50)
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#define OFFSET_SPI_DMARDL (0x54)
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#define OFFSET_SPI_IDR (0x58)
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#define OFFSET_SPI_SSI_COMPVER (0x5c)
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#define OFFSET_SPI_DR (0x60)
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#define SPI_FORMAT_MOTOROLA (0x00)
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#define SPI_FORMAT_TI (0x10)
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#define SPI_FORMAT_MICROWIRE (0x20)
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#define SPI_MODE_TX_RX (0x000)
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#define SPI_MODE_TX_ONLY (0x100)
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#define SPI_MODE_RX_ONLY (0x200)
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#define SPI_MODE_EEPROM (0x300)
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#define SPI_DATA_SIZE_4BIT (0x03)
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#define SPI_DATA_SIZE_5BIT (0x04)
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#define SPI_DATA_SIZE_6BIT (0x05)
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#define SPI_DATA_SIZE_7BIT (0x06)
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#define SPI_DATA_SIZE_8BIT (0x07)
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#define SPI_DATA_SIZE_9BIT (0x08)
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#define SPI_DATA_SIZE_10BIT (0x09)
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#define SPI_DATA_SIZE_16BIT (0x0f)
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#define SPI_POLARITY_HIGH (1<<7)
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#define SPI_POLARITY_LOW (0<<7)
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#define SPI_PHASE_RX_FIRST (0<<6)
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#define SPI_PHASE_TX_FIRST (1<<6)
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#define SPI_FIFO_DEPTH (32)
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#define SPI_IRQ_TXEIM (1<<0)
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#define SPI_IRQ_TXOIM (1<<1)
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#define SPI_IRQ_RXUIM (1<<2)
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#define SPI_IRQ_RXOIM (1<<3)
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#define SPI_IRQ_RXFIM (1<<4)
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#define SPI_IRQ_MSTIM (1<<5)
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#define SPI_IRQ_ALL (0x3f)
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#define SPI_ISR_FLAG (SPI_IRQ_TXEIM|SPI_IRQ_TXOIM|SPI_IRQ_RXUIM|SPI_IRQ_RXOIM)
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#define SPI_ISR_ERROR (SPI_IRQ_TXOIM | SPI_IRQ_RXUIM | SPI_IRQ_RXOIM)
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#define SPI_STATUS_BUSY (1)
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#define SPI_TX_DMA (1<<1)
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#define SPI_RX_DMA (1<<0)
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struct spi_config
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{
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rt_uint32_t frame_format;
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rt_uint32_t transfer_mode;
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rt_uint32_t clk_polarity;
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rt_uint32_t clk_phase;
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rt_uint32_t data_size;
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rt_uint32_t clk_div;
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};
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struct fh_spi_obj
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{
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rt_uint32_t id;
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rt_uint32_t irq;
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rt_uint32_t base;
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rt_uint32_t fifo_len;
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rt_uint32_t transfered_len;
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rt_uint32_t received_len;
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rt_uint32_t cs_gpio_pin;
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struct spi_config config;
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};
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void SPI_EnableSlaveen(struct fh_spi_obj *spi_obj, rt_uint32_t port);
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void SPI_DisableSlaveen(struct fh_spi_obj *spi_obj, rt_uint32_t port);
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void SPI_SetTxLevel(struct fh_spi_obj *spi_obj, rt_uint32_t level);
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void SPI_EnableIrq(struct fh_spi_obj *spi_obj, rt_uint32_t flag);
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void SPI_DisableIrq(struct fh_spi_obj *spi_obj, rt_uint32_t flag);
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rt_uint32_t SPI_InterruptStatus(struct fh_spi_obj *spi_obj);
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void SPI_ClearInterrupt(struct fh_spi_obj *spi_obj);
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rt_uint32_t SPI_ReadTxFifoLevel(struct fh_spi_obj *spi_obj);
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rt_uint32_t SPI_ReadRxFifoLevel(struct fh_spi_obj *spi_obj);
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UINT8 SPI_ReadData(struct fh_spi_obj *spi_obj);
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void SPI_WriteData(struct fh_spi_obj *spi_obj, UINT8 data);
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rt_uint32_t SPI_ReadStatus(struct fh_spi_obj *spi_obj);
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void SPI_Enable(struct fh_spi_obj *spi_obj, int enable);
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void SPI_SetParameter(struct fh_spi_obj *spi_obj);
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void SPI_EnableDma(struct fh_spi_obj *spi_obj, rt_uint32_t channel);
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void SPI_DisableDma(struct fh_spi_obj *spi_obj, rt_uint32_t channel);
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void SPI_WriteTxDmaLevel(struct fh_spi_obj *spi_obj, rt_uint32_t data);
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void SPI_WriteRxDmaLevel(struct fh_spi_obj *spi_obj, rt_uint32_t data);
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#endif /* FH_SPI_H_ */
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