252 lines
11 KiB
C
252 lines
11 KiB
C
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/*
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** ###################################################################
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** Processors: MK64FN1M0CAJ12
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** MK64FN1M0VDC12
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** MK64FN1M0VLL12
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** MK64FN1M0VLQ12
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** MK64FN1M0VMD12
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** MK64FX512VDC12
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** MK64FX512VLL12
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** MK64FX512VLQ12
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** MK64FX512VMD12
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**
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** Compilers: Keil ARM C/C++ Compiler
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** Freescale C/C++ for Embedded ARM
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** GNU C Compiler
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** IAR ANSI C/C++ Compiler for ARM
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** MCUXpresso Compiler
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**
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** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
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** Version: rev. 2.9, 2016-03-21
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** Build: b170112
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**
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** Abstract:
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** Provides a system configuration function and a global variable that
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** contains the system frequency. It configures the device and initializes
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** the oscillator (PLL) that is part of the microcontroller device.
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**
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** Copyright (c) 2016 Freescale Semiconductor, Inc.
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** Copyright 2016 - 2017 NXP
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** Redistribution and use in source and binary forms, with or without modification,
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** are permitted provided that the following conditions are met:
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**
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** o Redistributions of source code must retain the above copyright notice, this list
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** of conditions and the following disclaimer.
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**
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** o Redistributions in binary form must reproduce the above copyright notice, this
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** list of conditions and the following disclaimer in the documentation and/or
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** other materials provided with the distribution.
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**
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** o Neither the name of the copyright holder nor the names of its
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** contributors may be used to endorse or promote products derived from this
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** software without specific prior written permission.
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**
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** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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**
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** http: www.nxp.com
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** mail: support@nxp.com
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**
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** Revisions:
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** - rev. 1.0 (2013-08-12)
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** Initial version.
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** - rev. 2.0 (2013-10-29)
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** Register accessor macros added to the memory map.
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** Symbols for Processor Expert memory map compatibility added to the memory map.
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** Startup file for gcc has been updated according to CMSIS 3.2.
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** System initialization updated.
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** MCG - registers updated.
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** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
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** - rev. 2.1 (2013-10-30)
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** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
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** - rev. 2.2 (2013-12-09)
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** DMA - EARS register removed.
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** AIPS0, AIPS1 - MPRA register updated.
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** - rev. 2.3 (2014-01-24)
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** Update according to reference manual rev. 2
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** ENET, MCG, MCM, SIM, USB - registers updated
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** - rev. 2.4 (2014-02-10)
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** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
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** Update of SystemInit() and SystemCoreClockUpdate() functions.
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** - rev. 2.5 (2014-02-10)
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** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
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** Update of SystemInit() and SystemCoreClockUpdate() functions.
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** Module access macro module_BASES replaced by module_BASE_PTRS.
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** - rev. 2.6 (2014-08-28)
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** Update of system files - default clock configuration changed.
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** Update of startup files - possibility to override DefaultISR added.
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** - rev. 2.7 (2014-10-14)
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** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
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** - rev. 2.8 (2015-02-19)
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** Renamed interrupt vector LLW to LLWU.
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** - rev. 2.9 (2016-03-21)
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** Added MK64FN1M0CAJ12 part.
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** GPIO - renamed port instances: PTx -> GPIOx.
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**
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** ###################################################################
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*/
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/*!
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* @file MK64F12
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* @version 2.9
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* @date 2016-03-21
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* @brief Device specific configuration file for MK64F12 (implementation file)
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*
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* Provides a system configuration function and a global variable that contains
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* the system frequency. It configures the device and initializes the oscillator
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* (PLL) that is part of the microcontroller device.
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*/
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#include <stdint.h>
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#include "fsl_device_registers.h"
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/* ----------------------------------------------------------------------------
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-- Core clock
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---------------------------------------------------------------------------- */
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uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
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/* ----------------------------------------------------------------------------
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-- SystemInit()
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---------------------------------------------------------------------------- */
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void SystemInit (void) {
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#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
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SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
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#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
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#if (DISABLE_WDOG)
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/* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
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WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
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/* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
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WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
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/* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
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WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
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WDOG_STCTRLH_WAITEN_MASK |
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WDOG_STCTRLH_STOPEN_MASK |
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WDOG_STCTRLH_ALLOWUPDATE_MASK |
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WDOG_STCTRLH_CLKSRC_MASK |
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0x0100U;
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#endif /* (DISABLE_WDOG) */
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}
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/* ----------------------------------------------------------------------------
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-- SystemCoreClockUpdate()
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---------------------------------------------------------------------------- */
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void SystemCoreClockUpdate (void) {
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uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
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uint16_t Divider;
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if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
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/* Output of FLL or PLL is selected */
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if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
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/* FLL is selected */
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if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
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/* External reference clock is selected */
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switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
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case 0x00U:
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MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
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break;
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case 0x01U:
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MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
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break;
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case 0x02U:
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default:
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MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
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break;
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}
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if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
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switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
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case 0x38U:
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Divider = 1536U;
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break;
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case 0x30U:
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Divider = 1280U;
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break;
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default:
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Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
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break;
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}
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} else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
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Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
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}
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MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
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} else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
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MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
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} /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
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/* Select correct multiplier to calculate the MCG output clock */
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switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
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case 0x00U:
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MCGOUTClock *= 640U;
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break;
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case 0x20U:
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MCGOUTClock *= 1280U;
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break;
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case 0x40U:
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MCGOUTClock *= 1920U;
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break;
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case 0x60U:
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MCGOUTClock *= 2560U;
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break;
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case 0x80U:
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MCGOUTClock *= 732U;
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break;
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case 0xA0U:
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MCGOUTClock *= 1464U;
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break;
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case 0xC0U:
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MCGOUTClock *= 2197U;
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break;
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case 0xE0U:
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MCGOUTClock *= 2929U;
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break;
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default:
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break;
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}
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} else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
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/* PLL is selected */
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Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
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MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
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Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
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MCGOUTClock *= Divider; /* Calculate the MCG output clock */
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} /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
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} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
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/* Internal reference clock is selected */
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if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
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MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
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} else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
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Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
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MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
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} /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
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} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
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/* External reference clock is selected */
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switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
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case 0x00U:
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MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
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break;
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case 0x01U:
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MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
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break;
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case 0x02U:
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default:
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MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
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break;
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}
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} else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
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/* Reserved value */
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return;
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} /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
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SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
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}
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