441 lines
14 KiB
C
441 lines
14 KiB
C
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/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _FSL_GPIO_H_
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#define _FSL_GPIO_H_
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#include "fsl_common.h"
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/*!
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* @addtogroup gpio
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* @{
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*/
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @name Driver version */
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/*@{*/
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/*! @brief GPIO driver version 2.1.1. */
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#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
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/*@}*/
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/*! @brief GPIO direction definition */
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typedef enum _gpio_pin_direction
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{
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kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/
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kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/
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} gpio_pin_direction_t;
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#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
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/*! @brief GPIO checker attribute */
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typedef enum _gpio_checker_attribute
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{
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kGPIO_UsernonsecureRWUsersecureRWPrivilegedsecureRW =
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0x00U, /*!< User nonsecure:Read+Write; User Secure:Read+Write; Privileged Secure:Read+Write */
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kGPIO_UsernonsecureRUsersecureRWPrivilegedsecureRW =
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0x01U, /*!< User nonsecure:Read; User Secure:Read+Write; Privileged Secure:Read+Write */
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kGPIO_UsernonsecureNUsersecureRWPrivilegedsecureRW =
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0x02U, /*!< User nonsecure:None; User Secure:Read+Write; Privileged Secure:Read+Write */
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kGPIO_UsernonsecureRUsersecureRPrivilegedsecureRW =
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0x03U, /*!< User nonsecure:Read; User Secure:Read; Privileged Secure:Read+Write */
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kGPIO_UsernonsecureNUsersecureRPrivilegedsecureRW =
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0x04U, /*!< User nonsecure:None; User Secure:Read; Privileged Secure:Read+Write */
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kGPIO_UsernonsecureNUsersecureNPrivilegedsecureRW =
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0x05U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:Read+Write */
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kGPIO_UsernonsecureNUsersecureNPrivilegedsecureR =
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0x06U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:Read */
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kGPIO_UsernonsecureNUsersecureNPrivilegedsecureN =
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0x07U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:None */
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kGPIO_IgnoreAttributeCheck = 0x10U, /*!< Ignores the attribute check */
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} gpio_checker_attribute_t;
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#endif
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/*!
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* @brief The GPIO pin configuration structure.
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*
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* Each pin can only be configured as either an output pin or an input pin at a time.
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* If configured as an input pin, leave the outputConfig unused.
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* Note that in some use cases, the corresponding port property should be configured in advance
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* with the PORT_SetPinConfig().
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*/
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typedef struct _gpio_pin_config
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{
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gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */
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/* Output configurations; ignore if configured as an input pin */
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uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */
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} gpio_pin_config_t;
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/*! @} */
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/*******************************************************************************
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* API
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif
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/*!
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* @addtogroup gpio_driver
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* @{
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*/
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/*! @name GPIO Configuration */
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/*@{*/
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/*!
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* @brief Initializes a GPIO pin used by the board.
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*
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* To initialize the GPIO, define a pin configuration, as either input or output, in the user file.
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* Then, call the GPIO_PinInit() function.
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*
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* This is an example to define an input pin or an output pin configuration.
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* @code
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* // Define a digital input pin configuration,
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* gpio_pin_config_t config =
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* {
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* kGPIO_DigitalInput,
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* 0,
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* }
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* //Define a digital output pin configuration,
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* gpio_pin_config_t config =
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* {
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* kGPIO_DigitalOutput,
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* 0,
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* }
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* @endcode
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*
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* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
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* @param pin GPIO port pin number
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* @param config GPIO pin configuration pointer
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*/
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void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config);
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/*@}*/
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/*! @name GPIO Output Operations */
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/*@{*/
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/*!
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* @brief Sets the output level of the multiple GPIO pins to the logic 1 or 0.
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*
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* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
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* @param pin GPIO pin number
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* @param output GPIO pin output logic level.
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* - 0: corresponding pin output low-logic level.
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* - 1: corresponding pin output high-logic level.
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*/
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static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t pin, uint8_t output)
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{
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if (output == 0U)
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{
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base->PCOR = 1U << pin;
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}
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else
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{
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base->PSOR = 1U << pin;
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}
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}
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/*!
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* @brief Sets the output level of the multiple GPIO pins to the logic 1.
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*
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* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
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* @param mask GPIO pin number macro
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*/
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static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t mask)
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{
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base->PSOR = mask;
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}
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/*!
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* @brief Sets the output level of the multiple GPIO pins to the logic 0.
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*
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* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
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* @param mask GPIO pin number macro
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*/
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static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t mask)
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{
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base->PCOR = mask;
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}
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/*!
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* @brief Reverses the current output logic of the multiple GPIO pins.
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*
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* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
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* @param mask GPIO pin number macro
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*/
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static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t mask)
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{
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base->PTOR = mask;
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}
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/*@}*/
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/*! @name GPIO Input Operations */
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/*@{*/
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/*!
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* @brief Reads the current input value of the GPIO port.
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*
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* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
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* @param pin GPIO pin number
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* @retval GPIO port input value
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* - 0: corresponding pin input low-logic level.
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* - 1: corresponding pin input high-logic level.
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*/
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static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin)
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{
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return (((base->PDIR) >> pin) & 0x01U);
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}
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/*@}*/
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/*! @name GPIO Interrupt */
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/*@{*/
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/*!
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* @brief Reads the GPIO port interrupt status flag.
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*
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* If a pin is configured to generate the DMA request, the corresponding flag
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* is cleared automatically at the completion of the requested DMA transfer.
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* Otherwise, the flag remains set until a logic one is written to that flag.
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* If configured for a level sensitive interrupt that remains asserted, the flag
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* is set again immediately.
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*
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* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
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* @retval The current GPIO port interrupt status flag, for example, 0x00010001 means the
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* pin 0 and 17 have the interrupt.
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*/
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uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base);
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/*!
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* @brief Clears multiple GPIO pin interrupt status flags.
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*
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* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
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* @param mask GPIO pin number macro
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*/
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void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask);
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#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
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/*!
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* @brief The GPIO module supports a device-specific number of data ports, organized as 32-bit
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* words. Each 32-bit data port includes a GACR register, which defines the byte-level
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* attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data
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* bytes in the GACR follow a standard little endian
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* data convention.
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*
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* @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
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* @param mask GPIO pin number macro
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*/
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void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute);
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#endif
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/*@}*/
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/*! @} */
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/*!
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* @addtogroup fgpio_driver
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* @{
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*/
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/*
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* Introduces the FGPIO feature.
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*
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* The FGPIO features are only support on some Kinetis MCUs. The FGPIO registers are aliased to the IOPORT
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* interface. Accesses via the IOPORT interface occur in parallel with any instruction fetches and
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* complete in a single cycle. This aliased Fast GPIO memory map is called FGPIO.
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*/
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#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
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/*! @name FGPIO Configuration */
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/*@{*/
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/*!
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* @brief Initializes a FGPIO pin used by the board.
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*
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* To initialize the FGPIO driver, define a pin configuration, as either input or output, in the user file.
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* Then, call the FGPIO_PinInit() function.
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*
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* This is an example to define an input pin or an output pin configuration:
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* @code
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* // Define a digital input pin configuration,
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* gpio_pin_config_t config =
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* {
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* kGPIO_DigitalInput,
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* 0,
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* }
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* //Define a digital output pin configuration,
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* gpio_pin_config_t config =
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* {
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* kGPIO_DigitalOutput,
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* 0,
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* }
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* @endcode
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*
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* @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
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* @param pin FGPIO port pin number
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* @param config FGPIO pin configuration pointer
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*/
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void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config);
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/*@}*/
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/*! @name FGPIO Output Operations */
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/*@{*/
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/*!
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* @brief Sets the output level of the multiple FGPIO pins to the logic 1 or 0.
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*
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* @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
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* @param pin FGPIO pin number
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* @param output FGPIOpin output logic level.
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* - 0: corresponding pin output low-logic level.
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* - 1: corresponding pin output high-logic level.
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*/
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static inline void FGPIO_WritePinOutput(FGPIO_Type *base, uint32_t pin, uint8_t output)
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{
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if (output == 0U)
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{
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base->PCOR = 1 << pin;
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}
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else
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{
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base->PSOR = 1 << pin;
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}
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}
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/*!
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* @brief Sets the output level of the multiple FGPIO pins to the logic 1.
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*
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* @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
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* @param mask FGPIO pin number macro
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*/
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static inline void FGPIO_SetPinsOutput(FGPIO_Type *base, uint32_t mask)
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{
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base->PSOR = mask;
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}
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/*!
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* @brief Sets the output level of the multiple FGPIO pins to the logic 0.
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*
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* @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
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* @param mask FGPIO pin number macro
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*/
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static inline void FGPIO_ClearPinsOutput(FGPIO_Type *base, uint32_t mask)
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{
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base->PCOR = mask;
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}
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/*!
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* @brief Reverses the current output logic of the multiple FGPIO pins.
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*
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* @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
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* @param mask FGPIO pin number macro
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*/
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static inline void FGPIO_TogglePinsOutput(FGPIO_Type *base, uint32_t mask)
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{
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base->PTOR = mask;
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}
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/*@}*/
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/*! @name FGPIO Input Operations */
|
||
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|
/*@{*/
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||
|
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/*!
|
||
|
|
* @brief Reads the current input value of the FGPIO port.
|
||
|
|
*
|
||
|
|
* @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
|
||
|
|
* @param pin FGPIO pin number
|
||
|
|
* @retval FGPIO port input value
|
||
|
|
* - 0: corresponding pin input low-logic level.
|
||
|
|
* - 1: corresponding pin input high-logic level.
|
||
|
|
*/
|
||
|
|
static inline uint32_t FGPIO_ReadPinInput(FGPIO_Type *base, uint32_t pin)
|
||
|
|
{
|
||
|
|
return (((base->PDIR) >> pin) & 0x01U);
|
||
|
|
}
|
||
|
|
/*@}*/
|
||
|
|
|
||
|
|
/*! @name FGPIO Interrupt */
|
||
|
|
/*@{*/
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Reads the FGPIO port interrupt status flag.
|
||
|
|
*
|
||
|
|
* If a pin is configured to generate the DMA request, the corresponding flag
|
||
|
|
* is cleared automatically at the completion of the requested DMA transfer.
|
||
|
|
* Otherwise, the flag remains set until a logic one is written to that flag.
|
||
|
|
* If configured for a level-sensitive interrupt that remains asserted, the flag
|
||
|
|
* is set again immediately.
|
||
|
|
*
|
||
|
|
* @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
|
||
|
|
* @retval The current FGPIO port interrupt status flags, for example, 0x00010001 means the
|
||
|
|
* pin 0 and 17 have the interrupt.
|
||
|
|
*/
|
||
|
|
uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base);
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Clears the multiple FGPIO pin interrupt status flag.
|
||
|
|
*
|
||
|
|
* @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
|
||
|
|
* @param mask FGPIO pin number macro
|
||
|
|
*/
|
||
|
|
void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask);
|
||
|
|
|
||
|
|
#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
|
||
|
|
/*!
|
||
|
|
* @brief The FGPIO module supports a device-specific number of data ports, organized as 32-bit
|
||
|
|
* words. Each 32-bit data port includes a GACR register, which defines the byte-level
|
||
|
|
* attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data
|
||
|
|
* bytes in the GACR follow a standard little endian
|
||
|
|
* data convention.
|
||
|
|
*
|
||
|
|
* @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
|
||
|
|
* @param mask FGPIO pin number macro
|
||
|
|
*/
|
||
|
|
void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/*@}*/
|
||
|
|
|
||
|
|
#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */
|
||
|
|
|
||
|
|
#if defined(__cplusplus)
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
#endif /* _FSL_GPIO_H_*/
|