rtt-f030/bsp/stm32f10x/ssd1289.c

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#include "ssd1289.h"
// Compatible list:
// ssd1289
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#ifdef __CC_ARM /* ARM Compiler */
#define lcd_inline static __inline
#elif defined (__ICCARM__) /* for IAR Compiler */
#define lcd_inline inline
#elif defined (__GNUC__) /* GNU GCC Compiler */
#define lcd_inline static __inline
#else
#define lcd_inline static
#endif
#define rw_data_prepare() write_cmd(34)
/********* control ***********/
#include "stm32f10x.h"
#include "board.h"
//<2F><><EFBFBD><EFBFBD><EFBFBD>ض<EFBFBD><D8B6><EFBFBD>.<2E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ض<EFBFBD><D8B6><EFBFBD>ʱ.
#define printf rt_kprintf //ʹ<><CAB9>rt_kprintf<74><66><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
//#define printf(...) //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
/* LCD is connected to the FSMC_Bank1_NOR/SRAM2 and NE2 is used as ship select signal */
/* RS <==> A2 */
#define LCD_REG (*((volatile unsigned short *) 0x64000000)) /* RS = 0 */
#define LCD_RAM (*((volatile unsigned short *) 0x64000008)) /* RS = 1 */
static void LCD_FSMCConfig(void)
{
FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure;
FSMC_NORSRAMTimingInitTypeDef Timing_read,Timing_write;
/* FSMC GPIO configure */
{
GPIO_InitTypeDef GPIO_InitStructure;
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE | RCC_APB2Periph_GPIOF
| RCC_APB2Periph_GPIOG, ENABLE);
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
/*
FSMC_D0 ~ FSMC_D3
PD14 FSMC_D0 PD15 FSMC_D1 PD0 FSMC_D2 PD1 FSMC_D3
*/
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_14 | GPIO_Pin_15;
GPIO_Init(GPIOD,&GPIO_InitStructure);
/*
FSMC_D4 ~ FSMC_D12
PE7 ~ PE15 FSMC_D4 ~ FSMC_D12
*/
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10
| GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
GPIO_Init(GPIOE,&GPIO_InitStructure);
/* FSMC_D13 ~ FSMC_D15 PD8 ~ PD10 */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10;
GPIO_Init(GPIOD,&GPIO_InitStructure);
/*
FSMC_A0 ~ FSMC_A5 FSMC_A6 ~ FSMC_A9
PF0 ~ PF5 PF12 ~ PF15
*/
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3
| GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
GPIO_Init(GPIOF,&GPIO_InitStructure);
/* FSMC_A10 ~ FSMC_A15 PG0 ~ PG5 */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5;
GPIO_Init(GPIOG,&GPIO_InitStructure);
/* FSMC_A16 ~ FSMC_A18 PD11 ~ PD13 */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13;
GPIO_Init(GPIOD,&GPIO_InitStructure);
/* RD-PD4 WR-PD5 */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5;
GPIO_Init(GPIOD,&GPIO_InitStructure);
/* NBL0-PE0 NBL1-PE1 */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1;
GPIO_Init(GPIOE,&GPIO_InitStructure);
/* NE1/NCE2 */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;
GPIO_Init(GPIOD,&GPIO_InitStructure);
/* NE2 */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
GPIO_Init(GPIOG,&GPIO_InitStructure);
/* NE3 */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
GPIO_Init(GPIOG,&GPIO_InitStructure);
/* NE4 */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
GPIO_Init(GPIOG,&GPIO_InitStructure);
}
/* FSMC GPIO configure */
/*-- FSMC Configuration -------------------------------------------------*/
Timing_read.FSMC_AddressSetupTime = 30; /* <20><>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1> */
Timing_read.FSMC_DataSetupTime = 30; /* <20><><EFBFBD>ݽ<EFBFBD><DDBD><EFBFBD>ʱ<EFBFBD><CAB1> */
Timing_read.FSMC_AccessMode = FSMC_AccessMode_A; /* FSMC <20><><EFBFBD><EFBFBD>ģʽ */
Timing_write.FSMC_AddressSetupTime = 3; /* <20><>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1> */
Timing_write.FSMC_DataSetupTime = 3; /* <20><><EFBFBD>ݽ<EFBFBD><DDBD><EFBFBD>ʱ<EFBFBD><CAB1> */
Timing_write.FSMC_AccessMode = FSMC_AccessMode_A; /* FSMC <20><><EFBFBD><EFBFBD>ģʽ */
/* Color LCD configuration ------------------------------------
LCD configured as follow:
- Data/Address MUX = Disable
- Memory Type = SRAM
- Data Width = 16bit
- Write Operation = Enable
- Extended Mode = Enable
- Asynchronous Wait = Disable */
FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Enable;
FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &Timing_read;
FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &Timing_write;
FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE);
}
static void delay(int cnt)
{
volatile unsigned int dl;
while(cnt--)
{
for(dl=0; dl<500; dl++);
}
}
static void lcd_port_init(void)
{
LCD_FSMCConfig();
}
lcd_inline void write_cmd(unsigned short cmd)
{
LCD_REG = cmd;
}
lcd_inline unsigned short read_data(void)
{
return LCD_RAM;
}
lcd_inline void write_data(unsigned short data_code )
{
LCD_RAM = data_code;
}
lcd_inline void write_reg(unsigned char reg_addr,unsigned short reg_val)
{
write_cmd(reg_addr);
write_data(reg_val);
}
lcd_inline unsigned short read_reg(unsigned char reg_addr)
{
unsigned short val=0;
write_cmd(reg_addr);
val = read_data();
return (val);
}
/********* control <ֻ<><D6BB>ֲ<EFBFBD><D6B2><EFBFBD>Ϻ<EFBFBD><CFBA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>> ***********/
static unsigned short deviceid=0;//<2F><><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD>̬<EFBFBD><CCAC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>LCD<43><44>ID
//static unsigned short BGR2RGB(unsigned short c)
//{
// u16 r, g, b, rgb;
//
// b = (c>>0) & 0x1f;
// g = (c>>5) & 0x3f;
// r = (c>>11) & 0x1f;
//
// rgb = (b<<11) + (g<<5) + (r<<0);
//
// return( rgb );
//}
static void lcd_SetCursor(unsigned int x,unsigned int y)
{
write_reg(0x004e,x); /* 0-239 */
write_reg(0x004f,y); /* 0-319 */
}
/* <20><>ȡָ<C8A1><D6B8><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>GRAM */
static unsigned short lcd_read_gram(unsigned int x,unsigned int y)
{
unsigned short temp;
lcd_SetCursor(x,y);
rw_data_prepare();
/* dummy read */
temp = read_data();
temp = read_data();
return temp;
}
static void lcd_clear(unsigned short Color)
{
unsigned int index=0;
lcd_SetCursor(0,0);
rw_data_prepare(); /* Prepare to write GRAM */
for (index=0; index<(LCD_WIDTH*LCD_HEIGHT); index++)
{
write_data(Color);
}
}
static void lcd_data_bus_test(void)
{
unsigned short temp1;
unsigned short temp2;
// /* [5:4]-ID~ID0 [3]-AM-1<><31>ֱ-0ˮƽ */
// write_reg(0x0003,(1<<12)|(1<<5)|(1<<4) | (0<<3) );
/* wirte */
lcd_SetCursor(0,0);
rw_data_prepare();
write_data(0x5555);
lcd_SetCursor(1,0);
rw_data_prepare();
write_data(0xAAAA);
/* read */
lcd_SetCursor(0,0);
temp1 = lcd_read_gram(0,0);
temp2 = lcd_read_gram(1,0);
if( (temp1 == 0x5555) && (temp2 == 0xAAAA) )
{
printf(" data bus test pass!\r\n");
}
else
{
printf(" data bus test error: %04X %04X\r\n",temp1,temp2);
}
}
void ssd1289_init(void)
{
lcd_port_init();
deviceid = read_reg(0x00);
/* deviceid check */
if( deviceid != 0x8989 )
{
printf("Invalid LCD ID:%08X\r\n",deviceid);
printf("Please check you hardware and configure.\r\n");
}
else
{
printf("\r\nLCD Device ID : %04X ",deviceid);
}
// power supply setting
// set R07h at 0021h (GON=1,DTE=0,D[1:0]=01)
write_reg(0x0007,0x0021);
// set R00h at 0001h (OSCEN=1)
write_reg(0x0000,0x0001);
// set R07h at 0023h (GON=1,DTE=0,D[1:0]=11)
write_reg(0x0007,0x0023);
// set R10h at 0000h (Exit sleep mode)
write_reg(0x0010,0x0000);
// Wait 30ms
delay(3000);
// set R07h at 0033h (GON=1,DTE=1,D[1:0]=11)
write_reg(0x0007,0x0033);
// Entry mode setting (R11h)
// R11H Entry mode
// vsmode DFM1 DFM0 TRANS OEDef WMode DMode1 DMode0 TY1 TY0 ID1 ID0 AM LG2 LG2 LG0
// 0 1 1 0 0 0 0 0 0 1 1 1 * 0 0 0
write_reg(0x0011,0x6070);
// LCD driver AC setting (R02h)
write_reg(0x0002,0x0600);
// power control 1
// DCT3 DCT2 DCT1 DCT0 BT2 BT1 BT0 0 DC3 DC2 DC1 DC0 AP2 AP1 AP0 0
// 1 0 1 0 1 0 0 0 1 0 1 0 0 1 0 0
// DCT[3:0] fosc/4 BT[2:0] DC{3:0] fosc/4
write_reg(0x0003,0x0804);//0xA8A4
write_reg(0x000C,0x0000);//
write_reg(0x000D,0x0808);// 0x080C --> 0x0808
// power control 4
// 0 0 VCOMG VDV4 VDV3 VDV2 VDV1 VDV0 0 0 0 0 0 0 0 0
// 0 0 1 0 1 0 1 1 0 0 0 0 0 0 0 0
write_reg(0x000E,0x2900);
write_reg(0x001E,0x00B8);
write_reg(0x0001,0x2B3F);//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>320*240 0x6B3F
write_reg(0x0010,0x0000);
write_reg(0x0005,0x0000);
write_reg(0x0006,0x0000);
write_reg(0x0016,0xEF1C);
write_reg(0x0017,0x0003);
write_reg(0x0007,0x0233);//0x0233
write_reg(0x000B,0x0000|(3<<6));
write_reg(0x000F,0x0000);//ɨ<>ʼ<E8BFAA><CABC>ַ
write_reg(0x0041,0x0000);
write_reg(0x0042,0x0000);
write_reg(0x0048,0x0000);
write_reg(0x0049,0x013F);
write_reg(0x004A,0x0000);
write_reg(0x004B,0x0000);
write_reg(0x0044,0xEF00);
write_reg(0x0045,0x0000);
write_reg(0x0046,0x013F);
write_reg(0x0030,0x0707);
write_reg(0x0031,0x0204);
write_reg(0x0032,0x0204);
write_reg(0x0033,0x0502);
write_reg(0x0034,0x0507);
write_reg(0x0035,0x0204);
write_reg(0x0036,0x0204);
write_reg(0x0037,0x0502);
write_reg(0x003A,0x0302);
write_reg(0x003B,0x0302);
write_reg(0x0023,0x0000);
write_reg(0x0024,0x0000);
write_reg(0x0025,0x8000); // 65hz
write_reg(0x004f,0); // <20><><EFBFBD><EFBFBD>ַ0
write_reg(0x004e,0); // <20><><EFBFBD><EFBFBD>ַ0
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>߲<EFBFBD><DFB2><EFBFBD>,<2C><><EFBFBD>ڲ<EFBFBD><DAB2><EFBFBD>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƿ<EFBFBD><C7B7><EFBFBD><EFBFBD><EFBFBD>.
lcd_data_bus_test();
//GRAM<41><4D><EFBFBD><EFBFBD>,<2C>˲<EFBFBD><CBB2>Կ<EFBFBD><D4BF>Բ<EFBFBD><D4B2><EFBFBD>LCD<43><44><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD>GRAM.<2E><><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD>֤Ӳ<D6A4><D3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
// lcd_gram_test();
//<2F><><EFBFBD><EFBFBD>
lcd_clear( Blue );
}
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ص<EFBFBD> <20><>ɫ,X,Y */
void ssd1289_lcd_set_pixel(const char* pixel, int x, int y)
{
lcd_SetCursor(x,y);
rw_data_prepare();
write_data(*(rt_uint16_t*)pixel);
}
/* <20><>ȡ<EFBFBD><C8A1><EFBFBD>ص<EFBFBD><D8B5><EFBFBD>ɫ */
void ssd1289_lcd_get_pixel(char* pixel, int x, int y)
{
*(rt_uint16_t*)pixel = lcd_read_gram(x, y);
}
/* <20><>ˮƽ<CBAE><C6BD> */
void ssd1289_lcd_draw_hline(const char* pixel, int x1, int x2, int y)
{
/* [5:4]-ID~ID0 [3]-AM-1<><31>ֱ-0ˮƽ */
write_reg(0x0011,0x6030 | (0<<3)); // AM=0 hline
lcd_SetCursor(x1, y);
rw_data_prepare(); /* Prepare to write GRAM */
while (x1 < x2)
{
write_data(*(rt_uint16_t*)pixel);
x1++;
}
}
/* <20><>ֱ<EFBFBD><D6B1> */
void ssd1289_lcd_draw_vline(const char* pixel, int x, int y1, int y2)
{
/* [5:4]-ID~ID0 [3]-AM-1<><31>ֱ-0ˮƽ */
write_reg(0x0011,0x6070 | (1<<3)); // AM=0 vline
lcd_SetCursor(x, y1);
rw_data_prepare(); /* Prepare to write GRAM */
while (y1 < y2)
{
write_data(*(rt_uint16_t*)pixel);
y1++;
}
}
/* blit a line */
void ssd1289_lcd_blit_line(const char* pixels, int x, int y, rt_size_t size)
{
rt_uint16_t *ptr;
ptr = (rt_uint16_t*)pixels;
/* [5:4]-ID~ID0 [3]-AM-1<><31>ֱ-0ˮƽ */
write_reg(0x0011,0x6070 | (0<<3)); // AM=0 hline
lcd_SetCursor(x, y);
rw_data_prepare(); /* Prepare to write GRAM */
while (size)
{
write_data(*ptr ++);
size --;
}
}
struct rt_device_graphic_ops ssd1289_ops =
{
ssd1289_lcd_set_pixel,
ssd1289_lcd_get_pixel,
ssd1289_lcd_draw_hline,
ssd1289_lcd_draw_vline,
ssd1289_lcd_blit_line
};
struct rt_device _lcd_device;
static rt_err_t lcd_init(rt_device_t dev)
{
return RT_EOK;
}
static rt_err_t lcd_open(rt_device_t dev, rt_uint16_t oflag)
{
return RT_EOK;
}
static rt_err_t lcd_close(rt_device_t dev)
{
return RT_EOK;
}
static rt_err_t lcd_control(rt_device_t dev, rt_uint8_t cmd, void *args)
{
switch (cmd)
{
case RTGRAPHIC_CTRL_GET_INFO:
{
struct rt_device_graphic_info *info;
info = (struct rt_device_graphic_info*) args;
RT_ASSERT(info != RT_NULL);
info->bits_per_pixel = 16;
info->pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P;
info->framebuffer = RT_NULL;
info->width = 240;
info->height = 320;
}
break;
case RTGRAPHIC_CTRL_RECT_UPDATE:
/* nothong to be done */
break;
default:
break;
}
return RT_EOK;
}
void rt_hw_lcd_init(void)
{
/* LCD RESET */
/* PF10 : LCD RESET */
{
GPIO_InitTypeDef GPIO_InitStructure;
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOF, ENABLE);
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
GPIO_Init(GPIOF,&GPIO_InitStructure);
GPIO_ResetBits(GPIOF,GPIO_Pin_10);
GPIO_SetBits(GPIOF,GPIO_Pin_10);
/* wait for lcd reset */
rt_thread_delay(1);
}
/* register lcd device */
_lcd_device.type = RT_Device_Class_Graphic;
_lcd_device.init = lcd_init;
_lcd_device.open = lcd_open;
_lcd_device.close = lcd_close;
_lcd_device.control = lcd_control;
_lcd_device.read = RT_NULL;
_lcd_device.write = RT_NULL;
_lcd_device.user_data = &ssd1289_ops;
ssd1289_init();
/* register graphic device driver */
rt_device_register(&_lcd_device, "lcd",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STANDALONE);
}