178 lines
3.4 KiB
ArmAsm
178 lines
3.4 KiB
ArmAsm
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/*
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* File : start_gcc.S
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* Change Logs:
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* Date Author Notes
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* 2010-05-17 swkyer first version
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*/
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#include "../common/mips.inc"
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#include "../common/stackframe.h"
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#include "jz47xx.h"
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.section ".start", "ax"
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.set noreorder
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.extern sys_exception_handlers
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.extern tlbmiss_handle
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.globl _entry
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/* exception entry */
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_entry:
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.org 0x0
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.set noreorder
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mfc0 t0, $14
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jal tlbmiss_handle
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move a0, t0
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j _sys_dead /* TLB Miss, should never happen */
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nop
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.set reorder
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/*
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* void config_tick_timer(uint32_t perio)
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*/
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.globl config_tick_timer
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config_tick_timer:
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mfc0 t0, $9 /* count */
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nop
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addu t1, t0, a0
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mtc0 t1, $11 /* compare */
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jr ra
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nop
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.globl cp0_get_cause
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cp0_get_cause:
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mfc0 v0, CP0_CAUSE
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jr ra
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nop
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.globl cp0_get_status
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cp0_get_status:
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mfc0 v0, CP0_STATUS
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jr ra
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nop
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.globl cp0_get_hi
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cp0_get_hi:
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mfhi v0
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jr ra
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nop
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.globl cp0_get_lo
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cp0_get_lo:
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mflo v0
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jr ra
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nop
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.org 0x100
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.set noreorder
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j _sys_dead /* cache error exception handle */
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nop
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.set reorder
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.globl disable_cp0_counter
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disable_cp0_counter:
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.set noreorder
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mfc0 t0, CP0_CAUSE
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lui t1, 0x0800
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or t0, t1
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mtc0 t0, CP0_CAUSE
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jr ra
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nop
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.set reorder
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.globl enable_cp0_counter
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enable_cp0_counter:
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.set noreorder
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mfc0 t0, CP0_CAUSE
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lui t1, 0x0800
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not t2, t1
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and t0, t0, t2
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mtc0 t0, CP0_CAUSE
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jr ra
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nop
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.set reorder
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// general exception handle
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.org 0x180
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_gen_exp_handle:
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.set noreorder
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mfc0 k1, CP0_CAUSE
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andi k1, k1, 0x7c
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srl k1, k1, 2
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lw k0, sys_exception_handlers(k1)
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jr k0
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nop
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.set reorder
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/* error happens */
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_sys_dead:
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.set noreorder
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jal rt_hw_cpu_reset
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nop
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/* should never return here */
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j _sys_dead
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nop
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.set reorder
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.globl mips_irq_handle
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/* interrupt handle */
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.org 0x200
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_irq_handle:
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.set noreorder
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la k0, mips_irq_handle
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jr k0
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nop
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.set reorder
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/* the REAL program entry */
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.extern mips32_cfg_init
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.extern r4k_cache_init
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.extern install_default_execpt_handle
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.globl _start
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.org 0x400
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_start:
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.set noreorder
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la ra, _start
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/* init cp0 registers. */
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li t0, 0x0040FC00
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mtc0 t0, CP0_STATUS
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li t1, 0x00800000
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mtc0 t1, CP0_CAUSE
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/* setup stack pointer */
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li sp, SYSTEM_STACK
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la gp, _gp
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/* clear bss */
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la t0, __bss_start
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la t1, __bss_end
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_clr_bss_loop:
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sw zero, 0(t0)
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bne t0, t1, _clr_bss_loop
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addiu t0, t0, 4
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/* read core config */
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jal mips32_cfg_init
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nop
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/* initialize cache */
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jal r4k_cache_init
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nop
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/* setup default exception handle */
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jal install_default_execpt_handle
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nop
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/* jump to RT-Thread RTOS */
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jal rtthread_startup
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nop
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/* restart, never die */
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j _start
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nop
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.set reorder
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