102 lines
4.5 KiB
Plaintext
102 lines
4.5 KiB
Plaintext
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/*
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** ###################################################################
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** Processors: MIMXRT1052CVL5A
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** MIMXRT1052DVL6A
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**
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** Compiler: IAR ANSI C/C++ Compiler for ARM
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** Reference manual: IMXRT1050RM Rev.C, 08/2017
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** Version: rev. 0.1, 2017-01-10
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** Build: b170927
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**
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** Abstract:
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** Linker file for the IAR ANSI C/C++ Compiler for ARM
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**
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** Copyright 2016 Freescale Semiconductor, Inc.
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** Copyright 2016-2017 NXP
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** Redistribution and use in source and binary forms, with or without modification,
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** are permitted provided that the following conditions are met:
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**
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** 1. Redistributions of source code must retain the above copyright notice, this list
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** of conditions and the following disclaimer.
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**
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** 2. Redistributions in binary form must reproduce the above copyright notice, this
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** list of conditions and the following disclaimer in the documentation and/or
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** other materials provided with the distribution.
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**
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** 3. Neither the name of the copyright holder nor the names of its
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** contributors may be used to endorse or promote products derived from this
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** software without specific prior written permission.
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**
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** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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**
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** http: www.nxp.com
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** mail: support@nxp.com
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**
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** ###################################################################
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*/
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define symbol m_interrupts_start = 0x60002000;
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define symbol m_interrupts_end = 0x600023FF;
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define symbol m_text_start = 0x60002400;
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define symbol m_text_end = 0x7F7FFFFF;
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define symbol m_data_start = 0x20000000;
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define symbol m_data_end = 0x2001FFFF;
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define symbol m_data2_start = 0x20200000;
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define symbol m_data2_end = 0x2023FFFF;
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/* Sizes */
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if (isdefinedsymbol(__stack_size__)) {
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define symbol __size_cstack__ = __stack_size__;
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} else {
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define symbol __size_cstack__ = 0x0400;
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}
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if (isdefinedsymbol(__heap_size__)) {
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define symbol __size_heap__ = __heap_size__;
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} else {
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define symbol __size_heap__ = 0x0400;
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}
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define exported symbol __VECTOR_TABLE = m_interrupts_start;
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define exported symbol __VECTOR_RAM = m_interrupts_start;
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define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
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define memory mem with size = 4G;
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define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
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| mem:[from m_text_start to m_text_end];
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define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
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define region DATA2_region = mem:[from m_data2_start to m_data2_end];
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define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
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define block CSTACK with alignment = 8, size = __size_cstack__ { };
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define block HEAP with alignment = 8, size = __size_heap__ { };
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define block RW { readwrite };
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define block ZI { zi };
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define block NCACHE_VAR { section NonCacheable , section NonCacheable.init };
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initialize by copy { readwrite, section .textrw };
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do not initialize { section .noinit };
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place at address mem: m_interrupts_start { readonly section .intvec };
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place in TEXT_region { readonly };
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place in DATA_region { block RW };
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place in DATA_region { block ZI };
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place in DATA_region { last block HEAP };
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place in DATA_region { block NCACHE_VAR };
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place in CSTACK_region { block CSTACK };
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