102 lines
3.3 KiB
C
102 lines
3.3 KiB
C
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/*
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016 NXP
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_gpc.h"
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void GPC_EnableIRQ(GPC_Type *base, uint32_t irqId)
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{
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uint32_t irqRegNum = irqId / 32U;
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uint32_t irqRegShiftNum = irqId % 32U;
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assert(irqRegNum > 0U);
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assert(irqRegNum <= GPC_IMR_COUNT);
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#if ((defined FSL_FEATURE_GPC_HAS_IRQ_0_31) && FSL_FEATURE_GPC_HAS_IRQ_0_31)
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if (irqRegNum == GPC_IMR_COUNT)
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{
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base->IMR5 &= ~(1U << irqRegShiftNum);
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}
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else
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{
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base->IMR[irqRegNum] &= ~(1U << irqRegShiftNum);
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}
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#else
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base->IMR[irqRegNum - 1U] &= ~(1U << irqRegShiftNum);
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#endif /* FSL_FEATURE_GPC_HAS_IRQ_0_31 */
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}
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void GPC_DisableIRQ(GPC_Type *base, uint32_t irqId)
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{
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uint32_t irqRegNum = irqId / 32U;
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uint32_t irqRegShiftNum = irqId % 32U;
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assert(irqRegNum > 0U);
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assert(irqRegNum <= GPC_IMR_COUNT);
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#if ((defined FSL_FEATURE_GPC_HAS_IRQ_0_31) && FSL_FEATURE_GPC_HAS_IRQ_0_31)
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if (irqRegNum == GPC_IMR_COUNT)
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{
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base->IMR5 |= (1U << irqRegShiftNum);
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}
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else
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{
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base->IMR[irqRegNum] |= (1U << irqRegShiftNum);
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}
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#else
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base->IMR[irqRegNum - 1U] |= (1U << irqRegShiftNum);
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#endif /* FSL_FEATURE_GPC_HAS_IRQ_0_31 */
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}
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bool GPC_GetIRQStatusFlag(GPC_Type *base, uint32_t irqId)
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{
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uint32_t irqRegNum = irqId / 32U;
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uint32_t irqRegShiftNum = irqId % 32U;
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uint32_t ret;
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assert(irqRegNum > 0U);
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assert(irqRegNum <= GPC_IMR_COUNT);
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#if ((defined FSL_FEATURE_GPC_HAS_IRQ_0_31) && FSL_FEATURE_GPC_HAS_IRQ_0_31)
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if (irqRegNum == GPC_IMR_COUNT)
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{
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ret = base->ISR5 & (1U << irqRegShiftNum);
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}
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else
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{
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ret = base->ISR[irqRegNum] & (1U << irqRegShiftNum);
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}
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#else
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ret = base->ISR[irqRegNum - 1U] & (1U << irqRegShiftNum);
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#endif /* FSL_FEATURE_GPC_HAS_IRQ_0_31 */
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return (1U << irqRegShiftNum) == ret;
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}
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