266 lines
8.5 KiB
C
266 lines
8.5 KiB
C
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/*
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_cmt.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/* The standard intermediate frequency (IF). */
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#define CMT_INTERMEDIATEFREQUENCY_8MHZ (8000000U)
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/* CMT data modulate mask. */
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#define CMT_MODULATE_COUNT_WIDTH (8U)
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/* CMT diver 1. */
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#define CMT_CMTDIV_ONE (1)
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/* CMT diver 2. */
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#define CMT_CMTDIV_TWO (2)
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/* CMT diver 4. */
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#define CMT_CMTDIV_FOUR (4)
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/* CMT diver 8. */
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#define CMT_CMTDIV_EIGHT (8)
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Get instance number for CMT module.
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*
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* @param base CMT peripheral base address.
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*/
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static uint32_t CMT_GetInstance(CMT_Type *base);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/*! @brief Pointers to cmt clocks for each instance. */
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static const clock_ip_name_t s_cmtClock[FSL_FEATURE_SOC_CMT_COUNT] = CMT_CLOCKS;
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/*! @brief Pointers to cmt bases for each instance. */
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static CMT_Type *const s_cmtBases[] = CMT_BASE_PTRS;
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/*! @brief Pointers to cmt IRQ number for each instance. */
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static const IRQn_Type s_cmtIrqs[] = CMT_IRQS;
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/*******************************************************************************
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* Codes
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******************************************************************************/
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static uint32_t CMT_GetInstance(CMT_Type *base)
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{
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uint32_t instance;
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < ARRAY_SIZE(s_cmtBases); instance++)
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{
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if (s_cmtBases[instance] == base)
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{
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break;
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}
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}
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assert(instance < ARRAY_SIZE(s_cmtBases));
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return instance;
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}
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void CMT_GetDefaultConfig(cmt_config_t *config)
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{
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assert(config);
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/* Default infrared output is enabled and set with high active, the divider is set to 1. */
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config->isInterruptEnabled = false;
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config->isIroEnabled = true;
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config->iroPolarity = kCMT_IROActiveHigh;
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config->divider = kCMT_SecondClkDiv1;
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}
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void CMT_Init(CMT_Type *base, const cmt_config_t *config, uint32_t busClock_Hz)
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{
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assert(config);
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assert(busClock_Hz >= CMT_INTERMEDIATEFREQUENCY_8MHZ);
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uint8_t divider;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Ungate clock. */
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CLOCK_EnableClock(s_cmtClock[CMT_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/* Sets clock divider. The divider set in pps should be set
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to make sycClock_Hz/divder = 8MHz */
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base->PPS = CMT_PPS_PPSDIV(busClock_Hz / CMT_INTERMEDIATEFREQUENCY_8MHZ - 1);
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divider = base->MSC;
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divider &= ~CMT_MSC_CMTDIV_MASK;
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divider |= CMT_MSC_CMTDIV(config->divider);
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base->MSC = divider;
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/* Set the IRO signal. */
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base->OC = CMT_OC_CMTPOL(config->iroPolarity) | CMT_OC_IROPEN(config->isIroEnabled);
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/* Set interrupt. */
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if (config->isInterruptEnabled)
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{
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CMT_EnableInterrupts(base, kCMT_EndOfCycleInterruptEnable);
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EnableIRQ(s_cmtIrqs[CMT_GetInstance(base)]);
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}
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}
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void CMT_Deinit(CMT_Type *base)
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{
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/*Disable the CMT modulator. */
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base->MSC = 0;
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/* Disable the interrupt. */
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CMT_DisableInterrupts(base, kCMT_EndOfCycleInterruptEnable);
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DisableIRQ(s_cmtIrqs[CMT_GetInstance(base)]);
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Gate the clock. */
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CLOCK_DisableClock(s_cmtClock[CMT_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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void CMT_SetMode(CMT_Type *base, cmt_mode_t mode, cmt_modulate_config_t *modulateConfig)
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{
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uint8_t mscReg = base->MSC;
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/* Judge the mode. */
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if (mode != kCMT_DirectIROCtl)
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{
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assert(modulateConfig);
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/* Set carrier generator. */
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CMT_SetCarrirGenerateCountOne(base, modulateConfig->highCount1, modulateConfig->lowCount1);
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if (mode == kCMT_FSKMode)
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{
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CMT_SetCarrirGenerateCountTwo(base, modulateConfig->highCount2, modulateConfig->lowCount2);
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}
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/* Set carrier modulator. */
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CMT_SetModulateMarkSpace(base, modulateConfig->markCount, modulateConfig->spaceCount);
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mscReg &= ~ (CMT_MSC_FSK_MASK | CMT_MSC_BASE_MASK);
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mscReg |= mode;
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}
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else
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{
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mscReg &= ~CMT_MSC_MCGEN_MASK;
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}
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/* Set the CMT mode. */
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base->MSC = mscReg;
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}
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cmt_mode_t CMT_GetMode(CMT_Type *base)
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{
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uint8_t mode = base->MSC;
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if (!(mode & CMT_MSC_MCGEN_MASK))
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{ /* Carrier modulator disabled and the IRO signal is in direct software control. */
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return kCMT_DirectIROCtl;
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}
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else
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{
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/* Carrier modulator is enabled. */
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if (mode & CMT_MSC_BASE_MASK)
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{
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/* Base band mode. */
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return kCMT_BasebandMode;
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}
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else if (mode & CMT_MSC_FSK_MASK)
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{
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/* FSK mode. */
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return kCMT_FSKMode;
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}
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else
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{
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/* Time mode. */
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return kCMT_TimeMode;
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}
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}
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}
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uint32_t CMT_GetCMTFrequency(CMT_Type *base, uint32_t busClock_Hz)
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{
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uint32_t frequency;
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uint32_t divider;
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/* Get intermediate frequency. */
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frequency = busClock_Hz / ((base->PPS & CMT_PPS_PPSDIV_MASK) + 1);
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/* Get the second divider. */
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divider = ((base->MSC & CMT_MSC_CMTDIV_MASK) >> CMT_MSC_CMTDIV_SHIFT);
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/* Get CMT frequency. */
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switch ((cmt_second_clkdiv_t)divider)
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{
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case kCMT_SecondClkDiv1:
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frequency = frequency / CMT_CMTDIV_ONE;
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break;
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case kCMT_SecondClkDiv2:
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frequency = frequency / CMT_CMTDIV_TWO;
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break;
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case kCMT_SecondClkDiv4:
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frequency = frequency / CMT_CMTDIV_FOUR;
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break;
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case kCMT_SecondClkDiv8:
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frequency = frequency / CMT_CMTDIV_EIGHT;
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break;
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default:
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frequency = frequency / CMT_CMTDIV_ONE;
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break;
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}
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return frequency;
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}
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void CMT_SetModulateMarkSpace(CMT_Type *base, uint32_t markCount, uint32_t spaceCount)
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{
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/* Set modulate mark. */
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base->CMD1 = (markCount >> CMT_MODULATE_COUNT_WIDTH) & CMT_CMD1_MB_MASK;
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base->CMD2 = (markCount & CMT_CMD2_MB_MASK);
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/* Set modulate space. */
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base->CMD3 = (spaceCount >> CMT_MODULATE_COUNT_WIDTH) & CMT_CMD3_SB_MASK;
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base->CMD4 = spaceCount & CMT_CMD4_SB_MASK;
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}
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void CMT_SetIroState(CMT_Type *base, cmt_infrared_output_state_t state)
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{
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uint8_t ocReg = base->OC;
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ocReg &= ~CMT_OC_IROL_MASK;
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ocReg |= CMT_OC_IROL(state);
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/* Set the infrared output signal control. */
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base->OC = ocReg;
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}
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