2013-01-08 22:40:58 +08:00
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/*
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*******************************************************************************
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* Copyright(C) NEC Electronics Corporation 2010
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* All rights reserved by NEC Electronics Corporation.
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* This program should be used on your own responsibility.
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* NEC Electronics Corporation assumes no responsibility for any losses
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* incurred by customers or third parties arising from the use of this file.
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*
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* This device driver was created by Applilet3 for V850ES/Jx3
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* 32-Bit Single-Chip Microcontrollers
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* Filename: CG_timer.h
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* Abstract: This file implements device driver for Timer module.
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* APIlib: Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010]
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* Device: uPD70F3746
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* Compiler: IAR Systems ICCV850
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* Creation date: 6/26/2010
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*******************************************************************************
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*/
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#ifndef _MDTIMER_
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#define _MDTIMER_
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/*
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*******************************************************************************
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** Register bit define
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*******************************************************************************
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*/
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/*
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TMP control register 0 (TPnCTL0)
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*/
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/* TMP operation control (TPnCE) */
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#define _00_TMP_OPERATION_DISABLE 0x00U /* disable internal operating clock operation (asynchronously reset TMPn) */
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#define _80_TMP_OPERATION_ENABLE 0x80U /* enable internal operating clock operation */
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/* Internal count clock selection (TPnCKS2 - TPnCKS0) */
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#define _00_TMP_INTERNAL_CLOCK0 0x00U /* fXX */
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#define _01_TMP_INTERNAL_CLOCK1 0x01U /* fXX/2 */
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#define _02_TMP_INTERNAL_CLOCK2 0x02U /* fXX/2^2 */
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#define _03_TMP_INTERNAL_CLOCK3 0x03U /* fXX/2^3 */
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#define _04_TMP_INTERNAL_CLOCK4 0x04U /* fXX/2^4 */
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#define _05_TMP_INTERNAL_CLOCK5 0x05U /* fXX/2^5 */
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#define _06_TMP_INTERNAL_CLOCK6 0x06U /* fXX/2^6 or fXX/2^8 */
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#define _07_TMP_INTERNAL_CLOCK7 0x07U /* fXX/2^7 or fXX/2^9 */
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/*
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TMP control register 1 (TPnCTL1)
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*/
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/* Software trigger control (TPnEST) */
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#define _00_TMP_SOFTTRIGGER_OFF 0x00U /* no operation */
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#define _40_TMP_SOFTTRIGGER_ON 0x40U /* in one-shot pulse mode: One-shot pulse software trigger */
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/* in external trigger pulse output mode: Pulse output software trigger */
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/* Count clock selection (TPnEEE) */
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#define _00_TMP_INTERNAL_CLOCK 0x00U /* use the internal clock (clock selected with bits TPnCKS2 to TPnCKS0) */
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#define _20_TMP_EXTERNAL_CLOCK 0x20U /* use the external clock from the TIPn0 input pin */
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/* Timer mode selection (TPnMD2 - TPnMD0) */
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#define _00_TMP_MODE_INTERVAL 0x00U /* interval timer mode */
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#define _01_TMP_MODE_EXTERNALCOUNT 0x01U /* external event counter mode */
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#define _02_TMP_MODE_EXTERNALTRG 0x02U /* external trigger pulse output mode */
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#define _03_TMP_MODE_ONESHOT 0x03U /* one-shot pulse mode */
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#define _04_TMP_MODE_PWM 0x04U /* PWM mode */
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#define _05_TMP_MODE_FREERUNNING 0x05U /* free-running mode */
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#define _06_TMP_MODE_PULSEMEASURE 0x06U /* pulse width measurement mode */
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/*
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TMP I/O control register 0 (TPnIOC0)
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*/
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/* TOPn0 pin output level setting (TPnOL0) */
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#define _00_TMP_OUTPUT0_NORMAL 0x00U /* normal output */
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#define _02_TMP_OUTPUT0_INVERTED 0x02U /* inverted output */
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/* TOPn0 pin output setting (TPnOE0) */
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#define _00_TMP_OUTPUT0_DISABLE 0x00U /* disable timer output */
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#define _01_TMP_OUTPUT0_ENABLE 0x01U /* enable timer output (TOPn0 pin outputs pulses) */
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/* TOPn1 pin output level setting (TPnOL1) */
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#define _00_TMP_OUTPUT1_NORMAL 0x00U /* normal output */
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#define _08_TMP_OUTPUT1_INVERTED 0x08U /* inverted output */
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/* TOPn1 pin output setting (TPnOE1) */
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#define _00_TMP_OUTPUT1_DISABLE 0x00U /* disable timer output */
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#define _04_TMP_OUTPUT1_ENABLE 0x04U /* enable timer output (TOPn1 pin outputs pulses) */
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/*
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TMP I/O control register 1 (TPnIOC1)
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*/
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/* Capture trigger input signal (TIPn1 pin) valid edge setting (TPnIS3,TPnIS2) */
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#define _00_TMP_INPUT1_EDGE_NONE 0x00U /* detect no edge (capture operation is invalid) */
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#define _04_TMP_INPUT1_EDGE_RISING 0x04U /* detection of rising edge */
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#define _08_TMP_INPUT1_EDGE_FALLING 0x08U /* detection of falling edge */
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#define _0C_TMP_INPUT1_EDGE_BOTH 0x0CU /* detection of both edges */
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/* Capture trigger input signal (TIPn0 pin) valid edge setting (TPnIS1,TPnIS0) */
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#define _00_TMP_INPUT0_EDGE_NONE 0x00U /* detect no edge (capture operation is invalid) */
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#define _01_TMP_INPUT0_EDGE_RISING 0x01U /* detection of rising edge */
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#define _02_TMP_INPUT0_EDGE_FALLING 0x02U /* detection of falling edge */
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#define _03_TMP_INPUT0_EDGE_BOTH 0x03U /* detection of both edges */
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/*
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TMP I/O control register 2 (TPnIOC2)
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*/
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/* External event count input signal (TIPn0 pin) valid edge setting (TPnEES1,TPnEES0) */
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#define _00_TMP_EXTCOUNT_EDGE_NONE 0x00U /* detect no edge (external event count is invalid) */
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#define _04_TMP_EXTCOUNT_EDGE_RISING 0x04U /* detection of rising edge */
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#define _08_TMP_EXTCOUNT_EDGE_FALLING 0x08U /* detection of falling edge */
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#define _0C_TMP_EXTCOUNT_EDGE_BOTH 0x0CU /* detection of both edges */
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/* External trigger input signal (TIPn0 pin) valid edge setting (TPnETS1,TPnETS0) */
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#define _00_TMP_EXTTRIGGER_EDGE_NONE 0x00U /* detect no edge (external trigger is invalid) */
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#define _01_TMP_EXTTRIGGER_EDGE_RISING 0x01U /* detection of rising edge */
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#define _02_TMP_EXTTRIGGER_EDGE_FALLING 0x02U /* detection of falling edge */
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#define _03_TMP_EXTTRIGGER_EDGE_BOTH 0x03U /* detection of both edges */
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/*
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TMP option register 0 (TPnOPT0)
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*/
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/* TPnCCR1 register capture/compare selection (TPnCCS1) */
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#define _00_TMP_CCR1_COMPARE 0x00U /* compare register */
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#define _20_TMP_CCR1_CAPTURE 0x20U /* capture register */
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/* TPnCCR0 register capture/compare selection (TPnCCS0) */
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#define _00_TMP_CCR0_COMPARE 0x00U /* compare register */
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#define _10_TMP_CCR0_CAPTURE 0x10U /* capture register */
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/* TMPn overflow detection flag (TPnOVF) */
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#define _01_TMP_OVERFLOW_OCCUR 0x01U /* overflow occurred */
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#define _00_TMP_OVERFLOW_CLEAR 0x00U /* clear overflow */
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/*
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TMQ0 control register 0 (TQ0CTL0)
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*/
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/* TMQ operation control (TQ0CE) */
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#define _00_TMQ_OPERATION_DISABLE 0x00U /* disable internal operating clock operation (asynchronously reset TMQ0) */
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#define _80_TMQ_OPERATION_ENABLE 0x80U /* enable internal operating clock operation */
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/* Internal count clock selection (TQ0CKS2 - TQ0CKS0) */
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#define _00_TMQ_INTERNAL_CLOCK0 0x00U /* fXX */
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#define _01_TMQ_INTERNAL_CLOCK1 0x01U /* fXX/2 */
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#define _02_TMQ_INTERNAL_CLOCK2 0x02U /* fXX/2^2 */
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#define _03_TMQ_INTERNAL_CLOCK3 0x03U /* fXX/2^3 */
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#define _04_TMQ_INTERNAL_CLOCK4 0x04U /* fXX/2^4 */
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#define _05_TMQ_INTERNAL_CLOCK5 0x05U /* fXX/2^5 */
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#define _06_TMQ_INTERNAL_CLOCK6 0x06U /* fXX/2^6 */
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#define _07_TMQ_INTERNAL_CLOCK7 0x07U /* fXX/2^7 */
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/*
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TMQ0 control register 1 (TQ0CTL1)
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*/
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/* Software trigger control (TQ0EST) */
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#define _00_TMQ_SOFTTRIGGER_OFF 0x00U /* no operation */
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#define _40_TMQ_SOFTTRIGGER_ON 0x40U /* in one-shot pulse mode: One-shot pulse software trigger */
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/* in external trigger pulse output mode: Pulse output software trigger */
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/* Count clock selection (TQ0EEE) */
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#define _00_TMQ_INTERNAL_CLOCK 0x00U /* use the internal clock (clock selected with bits TQ0CKS2 to TQ0CKS0) */
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#define _20_TMQ_EXTERNAL_CLOCK 0x20U /* use the external clock from the TIQ00 input pin */
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/* Timer mode selection (TQ0MD2 - TQ0MD0) */
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#define _00_TMQ_MODE_INTERVAL 0x00U /* interval timer mode */
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#define _01_TMQ_MODE_EXTERNALCOUNT 0x01U /* external event counter mode */
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#define _02_TMQ_MODE_EXTERNALTRG 0x02U /* external trigger pulse output mode */
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#define _03_TMQ_MODE_ONESHOT 0x03U /* one-shot pulse mode */
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#define _04_TMQ_MODE_PWM 0x04U /* PWM mode */
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#define _05_TMQ_MODE_FREERUNNING 0x05U /* free-running mode */
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#define _06_TMQ_MODE_PULSEMEASURE 0x06U /* pulse width measurement mode */
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/*
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TMQ0 I/O control register 0 (TQ0IOC0)
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*/
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/* TOQ00 pin output level setting (TQ0OL0) */
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#define _00_TMQ_OUTPUT0_NORMAL 0x00U /* normal output */
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#define _02_TMQ_OUTPUT0_INVERTED 0x02U /* inverted output */
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/* TOQ00 pin output setting (TQ0OE0) */
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#define _00_TMQ_OUTPUT0_DISABLE 0x00U /* disable timer output */
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#define _01_TMQ_OUTPUT0_ENABLE 0x01U /* enable timer output (TOQ00 pin outputs pulses) */
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/* TOQ01 pin output level setting (TQ0OL1) */
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#define _00_TMQ_OUTPUT1_NORMAL 0x00U /* normal output */
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#define _08_TMQ_OUTPUT1_INVERTED 0x08U /* inverted output */
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/* TOQ01 pin output setting (TQ0OE1) */
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#define _00_TMQ_OUTPUT1_DISABLE 0x00U /* disable timer output */
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#define _04_TMQ_OUTPUT1_ENABLE 0x04U /* enable timer output (TOQ01 pin outputs pulses) */
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/* TOQ02 pin output level setting (TQ0OL2) */
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#define _00_TMQ_OUTPUT2_NORMAL 0x00U /* normal output */
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#define _20_TMQ_OUTPUT2_INVERTED 0x20U /* inverted output */
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/* TOQ02 pin output setting (TQ0OE2) */
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#define _00_TMQ_OUTPUT2_DISABLE 0x00U /* disable timer output */
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#define _10_TMQ_OUTPUT2_ENABLE 0x10U /* enable timer output (TOQ02 pin outputs pulses) */
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/* TOQ03 pin output level setting (TQ0OL3) */
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#define _00_TMQ_OUTPUT3_NORMAL 0x00U /* normal output */
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#define _80_TMQ_OUTPUT3_INVERTED 0x80U /* inverted output */
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/* TOQ03 pin output setting (TQ0OE3) */
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#define _00_TMQ_OUTPUT3_DISABLE 0x00U /* disable timer output */
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#define _40_TMQ_OUTPUT3_ENABLE 0x40U /* enable timer output (TOQ03 pin outputs pulses) */
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/*
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TMQ0 I/O control register 1 (TQ0IOC1)
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*/
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/* Capture trigger input signal (TIQ00 pin) valid edge setting (TQ0IS1,TQ0IS0) */
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#define _00_TMQ_INPUT0_EDGE_NONE 0x00U /* detect no edge (capture operation is invalid) */
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#define _01_TMQ_INPUT0_EDGE_RISING 0x01U /* detection of rising edge */
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#define _02_TMQ_INPUT0_EDGE_FALLING 0x02U /* detection of falling edge */
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#define _03_TMQ_INPUT0_EDGE_BOTH 0x03U /* detection of both edges */
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/* Capture trigger input signal (TIQ01 pin) valid edge setting (TQ0IS3,TQ0IS2) */
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#define _00_TMQ_INPUT1_EDGE_NONE 0x00U /* detect no edge (capture operation is invalid) */
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#define _04_TMQ_INPUT1_EDGE_RISING 0x04U /* detection of rising edge */
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#define _08_TMQ_INPUT1_EDGE_FALLING 0x08U /* detection of falling edge */
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#define _0C_TMQ_INPUT1_EDGE_BOTH 0x0CU /* detection of both edges */
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/* Capture trigger input signal (TIQ02 pin) valid edge setting (TQ0IS5,TQ0IS4) */
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#define _00_TMQ_INPUT2_EDGE_NONE 0x00U /* detect no edge (capture operation is invalid) */
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#define _10_TMQ_INPUT2_EDGE_RISING 0x10U /* detection of rising edge */
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#define _20_TMQ_INPUT2_EDGE_FALLING 0x20U /* detection of falling edge */
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#define _30_TMQ_INPUT2_EDGE_BOTH 0x30U /* detection of both edges */
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/* Capture trigger input signal (TIQ03 pin) valid edge setting (TQ0IS7,TQ0IS6) */
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#define _00_TMQ_INPUT3_EDGE_NONE 0x00U /* detect no edge (capture operation is invalid) */
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#define _40_TMQ_INPUT3_EDGE_RISING 0x40U /* detection of rising edge */
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#define _80_TMQ_INPUT3_EDGE_FALLING 0x80U /* detection of falling edge */
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#define _C0_TMQ_INPUT3_EDGE_BOTH 0xC0U /* detection of both edges */
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/*
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TMQ0 I/O control register 2 (TQ0IOC2)
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*/
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/* External event count input signal (TIQ00 pin) valid edge setting (TQ0EES1,TQ0EES0) */
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#define _00_TMQ_EXTCOUNT_EDGE_NONE 0x00U /* detect no edge (external event count is invalid) */
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#define _04_TMQ_EXTCOUNT_EDGE_RISING 0x04U /* detection of rising edge */
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#define _08_TMQ_EXTCOUNT_EDGE_FALLING 0x08U /* detection of falling edge */
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#define _0C_TMQ_EXTCOUNT_EDGE_BOTH 0x0CU /* detection of both edges */
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/* External trigger input signal (TIQ00 pin) valid edge setting (TQ0ETS1,TQ0ETS0) */
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#define _00_TMQ_EXTTRIGGER_EDGE_NONE 0x00U /* detect no edge (external trigger is invalid) */
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#define _01_TMQ_EXTTRIGGER_EDGE_RISING 0x01U /* detection of rising edge */
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#define _02_TMQ_EXTTRIGGER_EDGE_FALLING 0x02U /* detection of falling edge */
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#define _03_TMQ_EXTTRIGGER_EDGE_BOTH 0x03U /* detection of both edges */
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/*
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TMQ0 option register 0 (TQ0OPT0)
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*/
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/* TQ0CCR3 register capture/compare selection (TQ0CCS3) */
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#define _00_TMQ_CCR3_COMPARE 0x00U /* compare register */
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#define _80_TMQ_CCR3_CAPTURE 0x80U /* capture register */
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/* TQ0CCR2 register capture/compare selection (TQ0CCS2) */
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#define _00_TMQ_CCR2_COMPARE 0x00U /* compare register */
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#define _40_TMQ_CCR2_CAPTURE 0x40U /* capture register */
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/* TQ0CCR1 register capture/compare selection (TQ0CCS1) */
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#define _00_TMQ_CCR1_COMPARE 0x00U /* compare register */
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#define _20_TMQ_CCR1_CAPTURE 0x20U /* capture register */
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/* TQ0CCR0 register capture/compare selection (TQ0CCS0) */
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#define _00_TMQ_CCR0_COMPARE 0x00U /* compare register */
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#define _10_TMQ_CCR0_CAPTURE 0x10U /* capture register */
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/* TMQ0 overflow detection flag (TQ0OVF) */
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#define _01_TMQ_OVERFLOW_OCCUR 0x01U /* overflow occurred */
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#define _00_TMQ_OVERFLOW_CLEAR 0x00U /* clear overflow */
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/*
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TMM0 control register 0 (TM0CTL0)
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*/
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/* TMM0 operation control (TM0CE) */
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#define _00_TMM_OPERATION_DISABLE 0x00U /* disable internal operating clock operation (asynchronously reset TMM0) */
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#define _80_TMM_OPERATION_ENABLE 0x80U /* enable internal operating clock operation */
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/* Internal count clock selection (TM0CKS2 - TM0CKS0) */
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#define _00_TMM_INTERNAL_CLOCK0 0x00U /* fXX */
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#define _01_TMM_INTERNAL_CLOCK1 0x01U /* fXX/2 */
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#define _02_TMM_INTERNAL_CLOCK2 0x02U /* fXX/4 */
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#define _03_TMM_INTERNAL_CLOCK3 0x03U /* fXX/64 */
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#define _04_TMM_INTERNAL_CLOCK4 0x04U /* fXX/512 */
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#define _05_TMM_INTERNAL_CLOCK5 0x05U /* INTWT */
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#define _06_TMM_INTERNAL_CLOCK6 0x06U /* fR/8 */
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#define _07_TMM_INTERNAL_CLOCK7 0x07U /* fXT */
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/*
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*******************************************************************************
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** Macro define
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*******************************************************************************
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*/
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/* TMP0 compare register 0 (TP0CCR0)*/
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#define _9C3F_TMP0_CCR0_VALUE 0x9C3FU
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enum TMChannel
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{
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TMCHANNEL0, TMCHANNEL1, TMCHANNEL2, TMCHANNEL3
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};
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/*
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*******************************************************************************
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** Function define
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*******************************************************************************
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*/
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void TAB0_Init(void);
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void TAB0_Start(void);
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void TAB0_Stop(void);
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MD_STATUS TAB0_ChangeTimerCondition(USHORT *array_reg, UCHAR array_num);
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__interrupt void MD_INTTP0CC0(void);
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/* Start user code for function. Do not edit comment generated here */
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/* End user code. Do not edit comment generated here */
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#endif
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