214 lines
7.9 KiB
C
214 lines
7.9 KiB
C
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/******************************************************************************
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* @file: system_LPC122x.c
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* @purpose: CMSIS Cortex-M0 Device Peripheral Access Layer Source File
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* for the NXP LPC122x Device Series
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* @version: V1.0
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* @date: 26. Nov. 2008
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*----------------------------------------------------------------------------
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*
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* Copyright (C) 2008 ARM Limited. All rights reserved.
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*
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* ARM Limited (ARM) is supplying this software for use with Cortex-M3
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* processor based microcontrollers. This file can be freely distributed
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* within development tools that are supporting such ARM based processors.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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******************************************************************************/
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#include <stdint.h>
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#include "LPC122x.h"
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/*
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//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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*/
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/*--------------------- Clock Configuration ----------------------------------
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//
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// <e> Clock Configuration
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// <h> System Controls and Status Register (SCS)
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// <o1.4> OSCRANGE: Main Oscillator Range Select
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// <0=> 1 MHz to 20 MHz
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// <1=> 15 MHz to 24 MHz
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// <e1.5> OSCEN: Main Oscillator Enable
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// </e>
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// </h>
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//
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// <h> Clock Source Select Register (CLKSRCSEL)
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// <o2.0..1> CLKSRC: PLL Clock Source Selection
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// <0=> Internal RC oscillator
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// <1=> Main oscillator
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// <2=> RTC oscillator
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// </h>
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//
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// <e3> PLL0 Configuration (Main PLL)
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// <h> PLL0 Configuration Register (PLL0CFG)
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// <i> F_cco0 = (2 * M * F_in) / N
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// <i> F_in must be in the range of 32 kHz to 50 MHz
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// <i> F_cco0 must be in the range of 275 MHz to 550 MHz
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// <o4.0..14> MSEL: PLL Multiplier Selection
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// <6-32768><#-1>
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// <i> M Value
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// <o4.16..23> NSEL: PLL Divider Selection
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// <1-256><#-1>
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// <i> N Value
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// </h>
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// </e>
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//
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//
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// <h> CPU Clock Configuration Register (CCLKCFG)
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// <o7.0..7> CCLKSEL: Divide Value for CPU Clock from PLL0
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// <0-255>
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// <i> Divide is CCLKSEL + 1. Only 0 and odd values are valid.
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// </h>
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//
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//
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// </e>
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*/
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#define CLOCK_SETUP 1
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#define SYS_PLL_SETUP 1
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#define SYS_PLLSRCSEL_Val 0x00000001
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#define SYS_PLL_M_Val 0x00000003
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#define SYS_PLL_P_Val 0x00000001
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#define MAIN_CLKSRCSEL_Val 0x00000003
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#define SYS_AHB_DIV_Val 0x01 /* 1 through 255, 0 will disable the output. */
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/*
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//-------- <<< end of configuration section >>> ------------------------------
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*/
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/*----------------------------------------------------------------------------
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DEFINES
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*----------------------------------------------------------------------------*/
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/*----------------------------------------------------------------------------
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Define clocks
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*----------------------------------------------------------------------------*/
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#define XTAL (12000000UL) /* Oscillator frequency */
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#define OSC_CLK ( XTAL) /* Main oscillator frequency */
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#define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */
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#define WDT_OSC ( 250000UL) /* WDT oscillator frequency */
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/*----------------------------------------------------------------------------
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Clock Variable definitions
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*----------------------------------------------------------------------------*/
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uint32_t ClockSource = IRC_OSC;
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uint32_t SystemFrequency = IRC_OSC; /*!< System Clock Frequency (Core Clock) */
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uint32_t SystemAHBFrequency = IRC_OSC;
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/**
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* Misc. clock generation modules
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*
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* @param none
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* @return none
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*
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* @brief Setup the microcontroller system.
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* Initialize the System and update the SystemFrequency variable.
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*/
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void SystemPLL_Setup ( void )
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{
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uint32_t regVal;
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LPC_SYSCON->PRESETCTRL &= ~0x00008000; /* Disable 1-Cycle Read Mode */
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ClockSource = OSC_CLK;
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LPC_SYSCON->SYSPLLCLKSEL = SYS_PLLSRCSEL_Val; /* Select system OSC */
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LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update clock source */
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LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* toggle Update register once */
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LPC_SYSCON->SYSPLLCLKUEN = 0x01;
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while ( !(LPC_SYSCON->SYSPLLCLKUEN & 0x01) ); /* Wait until updated */
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regVal = LPC_SYSCON->SYSPLLCTRL;
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regVal &= ~0x1FF;
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LPC_SYSCON->SYSPLLCTRL = (regVal | (SYS_PLL_P_Val<<5) | SYS_PLL_M_Val);
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/* Enable main system clock, main system clock bit 7 in PDRUNCFG. */
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LPC_SYSCON->PDRUNCFG &= ~(0x1<<7);
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while ( !(LPC_SYSCON->SYSPLLSTAT & 0x01) ); /* Wait until it's locked */
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LPC_SYSCON->MAINCLKSEL = MAIN_CLKSRCSEL_Val; /* Select PLL clock output */
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LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK clock source */
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LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle update register once */
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LPC_SYSCON->MAINCLKUEN = 0x01;
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while ( !(LPC_SYSCON->MAINCLKUEN & 0x01) ); /* Wait until updated */
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LPC_SYSCON->SYSAHBCLKDIV = SYS_AHB_DIV_Val; /* SYS AHB clock, 0 will disable output */
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#if SYS_PLL_SETUP
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/* If the SYS PLL output is selected as the main clock. Even if SYS PLL is
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configured and enabled, it doesn't mean it will be selected as the MAIN clock
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source. Be careful with MAINCLKSEL value. If SYS PLL is not selected, System
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Frequence should be the same as either IRC, external OSC(SYS), or WDT OSC clock. */
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SystemFrequency = ClockSource * (SYS_PLL_M_Val+1);
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#else
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SystemFrequency = ClockSource;
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#endif
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SystemAHBFrequency = (uint32_t)(SystemFrequency/SYS_AHB_DIV_Val);
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return;
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}
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/**
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* Initialize the system
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*
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* @param none
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* @return none
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*
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* @brief Setup the microcontroller system.
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* Initialize the System and update the SystemFrequency variable.
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*/
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void SystemInit (void)
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{
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uint32_t i;
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#ifdef __DEBUG_RAM
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LPC_SYSCON->SYSMEMREMAP = 0x1; /* remap to internal RAM */
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#else
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#ifdef __DEBUG_FLASH
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LPC_SYSCON->SYSMEMREMAP = 0x2; /* remap to internal flash */
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#endif
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#endif
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#if 1
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/* First, below lines are for debugging only. For future release, WDT is
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enabled by bootrom, thus, unless a feed to WDT continuously, or WDT timeout
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will occur. If it's happen, WDT interrupt will be pending until a INT_CLEAR
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is applied. Below logic is to prevent system from going to the WDT interrupt
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during debugging.
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Second, all the peripheral clocks seem to be enabled by bootrom, it's
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not consistent with the UM. In below lines, only SYS, ROM, RAM, FLASHREG,
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FLASHARRAY, and I2C are enabled per UM dated July 14th. */
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LPC_WDT->MOD = 0x00;
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LPC_WDT->FEED = 0xAA; /* Feeding sequence */
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LPC_WDT->FEED = 0x55;
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NVIC->ICPR[0] |= 0xFFFFFFFF;
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LPC_SYSCON->SYSAHBCLKCTRL = 0x00000001F;
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#endif
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#if (CLOCK_SETUP) /* Clock Setup */
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/* bit 0 default is crystal bypass,
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bit1 0=0~20Mhz crystal input, 1=15~50Mhz crystal input. */
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LPC_SYSCON->SYSOSCCTRL = 0x00;
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/* main system OSC run is cleared, bit 5 in PDRUNCFG register */
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LPC_SYSCON->PDRUNCFG &= ~(0x1<<5);
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/* Wait 200us for OSC to be stablized, no status
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indication, dummy wait. */
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for ( i = 0; i < 0x100; i++ );
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#if (SYS_PLL_SETUP)
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SystemPLL_Setup();
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#endif
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#endif /* endif CLOCK_SETUP */
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/* System clock to the IOCON needs to be enabled or
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most of the I/O related peripherals won't work. */
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LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);
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return;
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}
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