223 lines
6.4 KiB
C
223 lines
6.4 KiB
C
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/*""FILE COMMENT""*******************************************************
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* System Name : Serial Peripheral Interface API for RX62Nxx
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* File Name : r_pdl_spi.h
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* Version : 1.02
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* Contents : SPI API header
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* Customer :
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* Model :
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* Order :
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* CPU : RX
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* Compiler : RXC
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* OS : Nothing
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* Programmer :
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* Note :
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************************************************************************
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* Copyright, 2011. Renesas Electronics Corporation
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* and Renesas Solutions Corporation
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************************************************************************
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* History : 2011.04.08
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* : Ver 1.02
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* : CS-5 release.
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*""FILE COMMENT END""**************************************************/
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#ifndef R_PDL_SPI_H
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#define R_PDL_SPI_H
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#include "r_pdl_common_defs_RX62Nxx.h"
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/* Function prototypes */
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bool R_SPI_Create(
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uint8_t,
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uint32_t,
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uint32_t,
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uint32_t,
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uint32_t
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);
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bool R_SPI_Destroy(
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uint8_t
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);
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bool R_SPI_Command(
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uint8_t,
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uint8_t,
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uint32_t,
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uint8_t
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);
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bool R_SPI_Transfer(
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uint8_t,
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uint8_t,
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uint32_t *,
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uint32_t *,
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uint16_t,
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void *,
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uint8_t
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);
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bool R_SPI_Control(
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uint8_t,
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uint8_t,
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uint32_t
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);
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bool R_SPI_GetStatus(
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uint8_t,
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uint16_t *,
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uint16_t *
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);
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/* Connection mode */
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#define PDL_SPI_MODE_SPI_MASTER 0x00000001ul
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#define PDL_SPI_MODE_SPI_MULTI_MASTER 0x00000002ul
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#define PDL_SPI_MODE_SPI_SLAVE 0x00000004ul
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#define PDL_SCI_MODE_SYNC_MASTER 0x00000008ul
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#define PDL_SCI_MODE_SYNC_SLAVE 0x00000010ul
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/* Reception control */
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#define PDL_SPI_FULL_DUPLEX 0x00000020ul
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#define PDL_SPI_TRANSMIT_ONLY 0x00000040ul
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/* Pin selection and control */
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#define PDL_SPI_PIN_CMOS 0x00000080ul
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#define PDL_SPI_PIN_OPEN_DRAIN 0x00000100ul
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#define PDL_SPI_PIN_A 0x00000200ul
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#define PDL_SPI_PIN_B 0x00000400ul
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#define PDL_SPI_PIN_RSPCK_ENABLE 0x00000800ul
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#define PDL_SPI_PIN_RSPCK_DISABLE 0x00001000ul
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#define PDL_SPI_PIN_MOSI_ENABLE 0x00002000ul
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#define PDL_SPI_PIN_MOSI_DISABLE 0x00004000ul
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#define PDL_SPI_PIN_MISO_ENABLE 0x00008000ul
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#define PDL_SPI_PIN_MISO_DISABLE 0x00010000ul
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#define PDL_SPI_PIN_SSL0_LOW 0x00020000ul
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#define PDL_SPI_PIN_SSL0_HIGH 0x00040000ul
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#define PDL_SPI_PIN_SSL0_DISABLE 0x00080000ul
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#define PDL_SPI_PIN_SSL1_LOW 0x00100000ul
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#define PDL_SPI_PIN_SSL1_HIGH 0x00200000ul
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#define PDL_SPI_PIN_SSL1_DISABLE 0x00400000ul
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#define PDL_SPI_PIN_SSL2_LOW 0x00800000ul
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#define PDL_SPI_PIN_SSL2_HIGH 0x01000000ul
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#define PDL_SPI_PIN_SSL2_DISABLE 0x02000000ul
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#define PDL_SPI_PIN_SSL3_LOW 0x04000000ul
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#define PDL_SPI_PIN_SSL3_HIGH 0x08000000ul
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#define PDL_SPI_PIN_SSL3_DISABLE 0x10000000ul
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#define PDL_SPI_PIN_MOSI_IDLE_LAST 0x20000000ul
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#define PDL_SPI_PIN_MOSI_IDLE_LOW 0x40000000ul
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#define PDL_SPI_PIN_MOSI_IDLE_HIGH 0x80000000ul
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/* Buffer size */
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#define PDL_SPI_BUFFER_64 0x00000001ul
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#define PDL_SPI_BUFFER_128 0x00000002ul
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/* Frame configuration selection */
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#define PDL_SPI_FRAME_1_1 0x00000004ul
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#define PDL_SPI_FRAME_1_2 0x00000008ul
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#define PDL_SPI_FRAME_1_3 0x00000010ul
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#define PDL_SPI_FRAME_1_4 0x00000020ul
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#define PDL_SPI_FRAME_2_1 0x00000040ul
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#define PDL_SPI_FRAME_2_2 0x00000080ul
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#define PDL_SPI_FRAME_3 0x00000100ul
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#define PDL_SPI_FRAME_4 0x00000200ul
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#define PDL_SPI_FRAME_5 0x00000400ul
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#define PDL_SPI_FRAME_6 0x00000800ul
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#define PDL_SPI_FRAME_7 0x00001000ul
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#define PDL_SPI_FRAME_8 0x00002000ul
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/* Parity bit control */
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#define PDL_SPI_PARITY_NONE 0x00004000ul
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#define PDL_SPI_PARITY_EVEN 0x00008000ul
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#define PDL_SPI_PARITY_ODD 0x00010000ul
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/* Extended clock delay */
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#define PDL_SPI_CLOCK_DELAY_1 0x00000001ul
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#define PDL_SPI_CLOCK_DELAY_2 0x00000002ul
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#define PDL_SPI_CLOCK_DELAY_3 0x00000004ul
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#define PDL_SPI_CLOCK_DELAY_4 0x00000008ul
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#define PDL_SPI_CLOCK_DELAY_5 0x00000010ul
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#define PDL_SPI_CLOCK_DELAY_6 0x00000020ul
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#define PDL_SPI_CLOCK_DELAY_7 0x00000040ul
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#define PDL_SPI_CLOCK_DELAY_8 0x00000080ul
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/* Extended SSL negation delay */
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#define PDL_SPI_SSL_DELAY_1 0x00000100ul
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#define PDL_SPI_SSL_DELAY_2 0x00000200ul
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#define PDL_SPI_SSL_DELAY_3 0x00000400ul
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#define PDL_SPI_SSL_DELAY_4 0x00000800ul
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#define PDL_SPI_SSL_DELAY_5 0x00001000ul
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#define PDL_SPI_SSL_DELAY_6 0x00002000ul
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#define PDL_SPI_SSL_DELAY_7 0x00004000ul
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#define PDL_SPI_SSL_DELAY_8 0x00008000ul
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/* Extended next-access delay */
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#define PDL_SPI_NEXT_DELAY_1 0x00010000ul
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#define PDL_SPI_NEXT_DELAY_2 0x00020000ul
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#define PDL_SPI_NEXT_DELAY_3 0x00040000ul
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#define PDL_SPI_NEXT_DELAY_4 0x00080000ul
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#define PDL_SPI_NEXT_DELAY_5 0x00100000ul
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#define PDL_SPI_NEXT_DELAY_6 0x00200000ul
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#define PDL_SPI_NEXT_DELAY_7 0x00400000ul
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#define PDL_SPI_NEXT_DELAY_8 0x00800000ul
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/* Channel control */
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#define PDL_SPI_DISABLE 0x01u
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/* Loopback control */
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#define PDL_SPI_LOOPBACK_DISABLE 0x02u
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#define PDL_SPI_LOOPBACK_DIRECT 0x04u
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#define PDL_SPI_LOOPBACK_REVERSED 0x08u
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/* Clock phase and polarity */
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#define PDL_SPI_CLOCK_MODE_0 0x00000001ul
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#define PDL_SPI_CLOCK_MODE_1 0x00000002ul
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#define PDL_SPI_CLOCK_MODE_2 0x00000004ul
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#define PDL_SPI_CLOCK_MODE_3 0x00000008ul
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/* Clock division */
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#define PDL_SPI_DIV_1 0x00000010ul
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#define PDL_SPI_DIV_2 0x00000020ul
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#define PDL_SPI_DIV_4 0x00000040ul
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#define PDL_SPI_DIV_8 0x00000080ul
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/* SSL assertion */
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#define PDL_SPI_ASSERT_SSL0 0x00000100ul
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#define PDL_SPI_ASSERT_SSL1 0x00000200ul
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#define PDL_SPI_ASSERT_SSL2 0x00000400ul
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#define PDL_SPI_ASSERT_SSL3 0x00000800ul
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/* SSL negation */
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#define PDL_SPI_SSL_NEGATE 0x00001000ul
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#define PDL_SPI_SSL_KEEP 0x00002000ul
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/* Frame data length */
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#define PDL_SPI_LENGTH_8 0x00004000ul
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#define PDL_SPI_LENGTH_9 0x00008000ul
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#define PDL_SPI_LENGTH_10 0x00010000ul
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#define PDL_SPI_LENGTH_11 0x00020000ul
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#define PDL_SPI_LENGTH_12 0x00040000ul
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#define PDL_SPI_LENGTH_13 0x00080000ul
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#define PDL_SPI_LENGTH_14 0x00100000ul
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#define PDL_SPI_LENGTH_15 0x00200000ul
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#define PDL_SPI_LENGTH_16 0x00400000ul
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#define PDL_SPI_LENGTH_20 0x00800000ul
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#define PDL_SPI_LENGTH_24 0x01000000ul
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#define PDL_SPI_LENGTH_32 0x02000000ul
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/* Data transfer format */
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#define PDL_SPI_MSB_FIRST 0x04000000ul
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#define PDL_SPI_LSB_FIRST 0x08000000ul
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/* Extended timing selection */
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#define PDL_SPI_CLOCK_DELAY_MINIMUM 0x01u
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#define PDL_SPI_CLOCK_DELAY_EXTENDED 0x02u
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/* Extended timing selection */
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#define PDL_SPI_SSL_DELAY_MINIMUM 0x04u
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#define PDL_SPI_SSL_DELAY_EXTENDED 0x08u
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/* Next-access delay */
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#define PDL_SPI_NEXT_DELAY_MINIMUM 0x10u
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#define PDL_SPI_NEXT_DELAY_EXTENDED 0x20u
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/* DMAC / DTC trigger control */
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#define PDL_SPI_DMAC_DTC_TRIGGER_DISABLE 0x01u
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#define PDL_SPI_DMAC_TRIGGER_ENABLE 0x02u
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#define PDL_SPI_DTC_TRIGGER_ENABLE 0x04u
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#endif
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/* End of file */
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