204 lines
5.2 KiB
C
204 lines
5.2 KiB
C
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/*""FILE COMMENT""*******************************************************
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* System Name : I<EFBFBD>C API for RX62Nxx
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* File Name : r_pdl_iic.h
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* Version : 1.02
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* Contents : I<EFBFBD>C API header
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* Customer :
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* Model :
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* Order :
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* CPU : RX
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* Compiler : RXC
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* OS : Nothing
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* Programmer :
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* Note :
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************************************************************************
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* Copyright, 2011. Renesas Electronics Corporation
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* and Renesas Solutions Corporation
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************************************************************************
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* History : 2011.04.08
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* : Ver 1.02
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* : CS-5 release.
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*""FILE COMMENT END""**************************************************/
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#ifndef R_PDL_IIC_H
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#define R_PDL_IIC_H
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#include "r_pdl_common_defs_RX62Nxx.h"
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/* Function prototypes */
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bool R_IIC_Create(
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uint8_t,
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uint32_t,
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uint32_t,
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uint16_t,
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uint16_t,
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uint16_t,
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uint32_t,
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uint32_t
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);
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bool R_IIC_Destroy(
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uint8_t
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);
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bool R_IIC_MasterSend(
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uint8_t,
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uint16_t,
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uint16_t,
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uint8_t *,
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uint16_t,
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void *,
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uint8_t
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);
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bool R_IIC_MasterReceive(
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uint8_t,
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uint16_t,
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uint16_t,
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uint8_t *,
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uint16_t,
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void *,
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uint8_t
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);
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bool R_IIC_MasterReceiveLast(
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uint8_t,
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uint8_t *
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);
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bool R_IIC_SlaveMonitor(
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uint8_t,
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uint16_t,
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uint8_t *,
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uint16_t,
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void *,
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uint8_t
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);
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bool R_IIC_SlaveSend(
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uint8_t,
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uint8_t *,
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uint16_t
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);
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bool R_IIC_Control(
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uint8_t,
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uint8_t
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);
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bool R_IIC_GetStatus(
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uint8_t,
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uint32_t *,
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uint16_t *,
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uint16_t *
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);
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/* Bus mode */
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#define PDL_IIC_MODE_IIC 0x00000001ul
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#define PDL_IIC_MODE_IIC_FMP 0x00000002ul
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#define PDL_IIC_MODE_SMBUS 0x00000004ul
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/* Internal reference clock */
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#define PDL_IIC_INT_PCLK_DIV_1 0x00000008ul
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#define PDL_IIC_INT_PCLK_DIV_2 0x00000010ul
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#define PDL_IIC_INT_PCLK_DIV_4 0x00000020ul
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#define PDL_IIC_INT_PCLK_DIV_8 0x00000040ul
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#define PDL_IIC_INT_PCLK_DIV_16 0x00000080ul
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#define PDL_IIC_INT_PCLK_DIV_32 0x00000100ul
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#define PDL_IIC_INT_PCLK_DIV_64 0x00000200ul
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#define PDL_IIC_INT_PCLK_DIV_128 0x00000400ul
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/* Timeout detection */
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#define PDL_IIC_TIMEOUT_DISABLE 0x00000800ul
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#define PDL_IIC_TIMEOUT_LOW 0x00001000ul
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#define PDL_IIC_TIMEOUT_HIGH 0x00002000ul
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#define PDL_IIC_TIMEOUT_BOTH 0x00004000ul
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/* Timeout mode */
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#define PDL_IIC_TIMEOUT_LONG 0x00008000ul
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#define PDL_IIC_TIMEOUT_SHORT 0x00010000ul
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/* SDA output delay count */
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#define PDL_IIC_SDA_DELAY_0 0x00020000ul
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#define PDL_IIC_SDA_DELAY_1 0x00040000ul
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#define PDL_IIC_SDA_DELAY_2 0x00080000ul
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#define PDL_IIC_SDA_DELAY_3 0x00100000ul
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#define PDL_IIC_SDA_DELAY_4 0x00200000ul
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#define PDL_IIC_SDA_DELAY_5 0x00400000ul
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#define PDL_IIC_SDA_DELAY_6 0x00800000ul
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#define PDL_IIC_SDA_DELAY_7 0x01000000ul
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/* SDA output delay clock source */
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#define PDL_IIC_SDA_DELAY_DIV_1 0x02000000ul
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#define PDL_IIC_SDA_DELAY_DIV_2 0x04000000ul
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/* Noise filter control */
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#define PDL_IIC_NF_DISABLE 0x08000000ul
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#define PDL_IIC_NF_1 0x10000000ul
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#define PDL_IIC_NF_2 0x20000000ul
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#define PDL_IIC_NF_3 0x40000000ul
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#define PDL_IIC_NF_4 0x80000000ul
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/* NACK Transmission Arbitration Lost Detection control */
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#define PDL_IIC_NTALD_DISABLE 0x00000001ul
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#define PDL_IIC_NTALD_ENABLE 0x00000002ul
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/* Slave Arbitration Lost Detection control */
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#define PDL_IIC_SALD_DISABLE 0x00000004ul
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#define PDL_IIC_SALD_ENABLE 0x00000008ul
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/* Slave address detection control */
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#define PDL_IIC_SLAVE_0_DISABLE 0x00000010ul
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#define PDL_IIC_SLAVE_0_ENABLE_7 0x00000020ul
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#define PDL_IIC_SLAVE_0_ENABLE_10 0x00000040ul
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#define PDL_IIC_SLAVE_1_DISABLE 0x00000080ul
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#define PDL_IIC_SLAVE_1_ENABLE_7 0x00000100ul
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#define PDL_IIC_SLAVE_1_ENABLE_10 0x00000200ul
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#define PDL_IIC_SLAVE_2_DISABLE 0x00000400ul
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#define PDL_IIC_SLAVE_2_ENABLE_7 0x00000800ul
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#define PDL_IIC_SLAVE_2_ENABLE_10 0x00001000ul
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#define PDL_IIC_SLAVE_GCA_DISABLE 0x00002000ul
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#define PDL_IIC_SLAVE_GCA_ENABLE 0x00004000ul
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/* Device-ID detection control */
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#define PDL_IIC_DEVICE_ID_DISABLE 0x00008000ul
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#define PDL_IIC_DEVICE_ID_ENABLE 0x00010000ul
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/* Host Address detection control */
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#define PDL_IIC_HOST_ADDRESS_DISABLE 0x00020000ul
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#define PDL_IIC_HOST_ADDRESS_ENABLE 0x00040000ul
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/* Start / Repeated Start condition control */
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#define PDL_IIC_START_ENABLE 0x0001u
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#define PDL_IIC_START_DISABLE 0x0002u
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/* Stop condition control */
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#define PDL_IIC_STOP_ENABLE 0x0004u
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#define PDL_IIC_STOP_DISABLE 0x0008u
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/* Master DMAC / DTC trigger control */
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#define PDL_IIC_DMAC_DTC_TRIGGER_DISABLE 0x0010u
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#define PDL_IIC_DMAC_TRIGGER_ENABLE 0x0020u
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#define PDL_IIC_DTC_TRIGGER_ENABLE 0x0040u
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/* Slave DMAC / DTC trigger control */
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#define PDL_IIC_RX_DMAC_DTC_TRIGGER_DISABLE 0x0080u
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#define PDL_IIC_RX_DMAC_TRIGGER_ENABLE 0x0100u
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#define PDL_IIC_RX_DTC_TRIGGER_ENABLE 0x0200u
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#define PDL_IIC_TX_DMAC_DTC_TRIGGER_DISABLE 0x0400u
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#define PDL_IIC_TX_DMAC_TRIGGER_ENABLE 0x0800u
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#define PDL_IIC_TX_DTC_TRIGGER_ENABLE 0x1000u
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/* Stop generation */
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#define PDL_IIC_STOP 0x01u
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/* NACK generation */
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#define PDL_IIC_NACK 0x02u
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/* Pin control */
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#define PDL_IIC_SDA_LOW 0x04u
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#define PDL_IIC_SDA_HI_Z 0x08u
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#define PDL_IIC_SCL_LOW 0x10u
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#define PDL_IIC_SCL_HI_Z 0x20u
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/* Extra clock cycle generation */
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#define PDL_IIC_CYCLE_SCL 0x40u
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/* Reset control */
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#define PDL_IIC_RESET 0x80u
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#endif
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/* End of file */
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