515 lines
14 KiB
C
515 lines
14 KiB
C
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/*
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* File : drv_uart.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2015-11-19 Urey the first version
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include <rtdevice.h>
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#include <string.h>
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#include "board.h"
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#include "drv_uart.h"
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#include "drv_gpio.h"
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#include "drv_clock.h"
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struct jz_uart_s
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{
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rt_uint32_t hw_base;
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rt_uint32_t irqno;
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char name[RT_NAME_MAX];
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};
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static rt_err_t uart_configure (struct rt_serial_device *serial, struct serial_configure *cfg);
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static rt_err_t uart_control (struct rt_serial_device *serial, int cmd, void *arg);
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static int uart_putc (struct rt_serial_device *serial, char c);
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static int uart_getc (struct rt_serial_device *serial);
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static rt_size_t uart_dma_transmit (struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction);
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static void uart_irq_handler (int irqno, void *param);
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const struct rt_uart_ops _uart_ops =
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{
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uart_configure,
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uart_control,
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uart_putc,
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uart_getc,
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uart_dma_transmit
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};
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struct baudtoregs_t
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{
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unsigned int baud;
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unsigned short div;
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unsigned int umr:5;
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unsigned int uacr:12;
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};
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static struct baudtoregs_t baudtoregs[] =
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{
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/*
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The data is generated by a python,
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the script is tools/tty/get_divisor.py
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*/
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#if (BOARD_EXTAL_CLK == 24000000)
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{50,0x7530,0x10,0x0},
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{75,0x4e20,0x10,0x0},
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{110,0x3521,0x10,0x0},
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{134,0x2b9d,0x10,0x0},
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{150,0x2710,0x10,0x0},
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{200,0x1d4c,0x10,0x0},
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{300,0x1388,0x10,0x0},
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{600,0x9c4,0x10,0x0},
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{1200,0x4e2,0x10,0x0},
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{1800,0x340,0x10,0x0},
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{2400,0x271,0x10,0x0},
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{4800,0x138,0x10,0x0},
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{9600,0x9c,0x10,0x0},
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{19200,0x4e,0x10,0x0},
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{38400,0x27,0x10,0x0},
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{57600,0x1a,0x10,0x0},
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{115200,0xd,0x10,0x0},
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{230400,0x6,0x11,0x550},
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{460800,0x3,0x11,0x550},
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{500000,0x3,0x10,0x0},
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{576000,0x3,0xd,0x0},
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{921600,0x2,0xd,0x0},
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{1000000,0x2,0xc,0x0},
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{1152000,0x1,0x14,0x400},
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{1500000,0x1,0x10,0x0},
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{2000000,0x1,0xc,0x0},
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{2500000,0x1,0x9,0x780},
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{3000000,0x1,0x8,0x0},
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{3500000,0x1,0x6,0x400},
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{4000000,0x1,0x6,0x0},
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#elif (BOARD_EXTAL_CLK == 26000000)
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{50,0x7ef4,0x10,0x0},
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{75,0x546b,0x10,0x0},
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{110,0x398f,0x10,0x0},
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{134,0x2f40,0x10,0x0},
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{150,0x2a36,0x10,0x0},
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{200,0x1fbd,0x10,0x0},
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{300,0x151b,0x10,0x0},
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{600,0xa8e,0x10,0x0},
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{1200,0x547,0x10,0x0},
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{1800,0x385,0x10,0x0},
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{2400,0x2a4,0x10,0x0},
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{4800,0x152,0x10,0x0},
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{9600,0xa9,0x10,0x0},
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{19200,0x54,0x10,0x2},
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{38400,0x2a,0x10,0x2},
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{57600,0x1c,0x10,0x2},
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{115200,0xe,0x10,0x2},
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{230400,0x7,0x10,0x2},
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{460800,0x4,0xe,0x2},
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{500000,0x3,0x11,0x550},
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{576000,0x3,0xf,0x2},
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{921600,0x2,0xe,0x2},
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{1000000,0x2,0xd,0x0},
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{1152000,0x2,0xb,0x248},
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{1500000,0x1,0x11,0x550},
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{2000000,0x1,0xd,0x0},
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{2500000,0x1,0xa,0x2a0},
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{3000000,0x1,0x8,0x700},
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{3500000,0x1,0x7,0x2a0},
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{4000000,0x1,0x6,0x7c0},
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#elif (BOARD_EXTAL_CLK == 48000000)
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{50,0xea60,0x10,0x0},
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{75,0x9c40,0x10,0x0},
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{110,0x6a42,0x10,0x0},
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{134,0x573a,0x10,0x0},
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{150,0x4e20,0x10,0x0},
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{200,0x3a98,0x10,0x0},
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{300,0x2710,0x10,0x0},
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{600,0x1388,0x10,0x0},
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{1200,0x9c4,0x10,0x0},
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{1800,0x67f,0x10,0x0},
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{2400,0x4e2,0x10,0x0},
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{4800,0x271,0x10,0x0},
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{9600,0x138,0x10,0x0},
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{19200,0x9c,0x10,0x0},
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{38400,0x4e,0x10,0x0},
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{57600,0x34,0x10,0x0},
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{115200,0x1a,0x10,0x0},
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{230400,0xd,0x10,0x0},
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{460800,0x6,0x11,0x550},
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{500000,0x6,0x10,0x0},
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{576000,0x5,0x10,0x700},
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{921600,0x3,0x11,0x550},
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{1000000,0x3,0x10,0x0},
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{1152000,0x3,0xd,0x0},
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{1500000,0x2,0x10,0x0},
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{2000000,0x2,0xc,0x0},
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{2500000,0x1,0x13,0x84},
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{3000000,0x1,0x10,0x0},
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{3500000,0x1,0xd,0x600},
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{4000000,0x1,0xc,0x0},
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#endif
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};
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static unsigned short quot1[3] = {0}; /* quot[0]:baud_div, quot[1]:umr, quot[2]:uacr */
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static unsigned short *get_divisor(unsigned int baud)
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{
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struct baudtoregs_t *bt;
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int index;
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for (index = 0; index < sizeof(baudtoregs)/sizeof(baudtoregs[0]); index ++)
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{
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bt = &baudtoregs[index];
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if (bt->baud == baud)
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{
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break;
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}
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}
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if (index < sizeof(baudtoregs)/sizeof(baudtoregs[0]))
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{
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quot1[0] = bt->div;
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quot1[1] = bt->umr;
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quot1[2] = bt->uacr;
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return quot1;
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}
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return NULL;
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}
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/*
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* UART Initiation
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*/
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void rt_hw_uart_init(void)
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{
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struct rt_serial_device *serial;
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struct jz_uart_s *uart;
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struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
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#ifdef RT_USING_UART0 /* for BT */
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{
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static struct rt_serial_device serial0;
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static struct jz_uart_s uart0;
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serial = &serial0;
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uart = &uart0;
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serial->ops = &_uart_ops;
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serial->config = config;
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serial->config.bufsz = 2048;
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serial->config.baud_rate = 115200;
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uart->hw_base = UART0_BASE;
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uart->irqno = IRQ_UART0;
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strcpy(uart->name, "uart0");
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/* PC10/11/12/13 as RXD/TXD/RTS/CTS */
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gpio_set_func(GPIO_PORT_C, GPIO_Pin_10, GPIO_FUNC_0);
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gpio_set_func(GPIO_PORT_C, GPIO_Pin_11, GPIO_FUNC_0);
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gpio_set_func(GPIO_PORT_C, GPIO_Pin_12, GPIO_FUNC_0);
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gpio_set_func(GPIO_PORT_C, GPIO_Pin_13, GPIO_FUNC_0);
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clk_enable(clk_get("uart0"));
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{
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extern int uart0_clk(void);
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uart0_clk();
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}
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rt_hw_serial_register(serial,
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"uart0",
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RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
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uart);
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}
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#endif
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#ifdef RT_USING_UART1
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{
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static struct rt_serial_device serial1;
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static struct jz_uart_s uart1;
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serial = &serial1;
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uart = &uart1;
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strcpy(uart->name, "uart1");
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serial->ops = &_uart_ops;
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serial->config = config;
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serial->config.baud_rate = 115200;
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uart->hw_base = UART1_BASE;
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uart->irqno = IRQ_UART1;
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/* PD2/3/4/5 as RXD/TXD/RTS/CTS */
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gpio_set_func(GPIO_PORT_D, GPIO_Pin_2, GPIO_FUNC_1);
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gpio_set_func(GPIO_PORT_D, GPIO_Pin_3, GPIO_FUNC_1);
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gpio_set_func(GPIO_PORT_D, GPIO_Pin_4, GPIO_FUNC_1);
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gpio_set_func(GPIO_PORT_D, GPIO_Pin_5, GPIO_FUNC_1);
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clk_enable(clk_get("uart1"));
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{
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extern int uart1_clk(void);
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uart1_clk();
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}
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rt_hw_serial_register(serial,
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"uart1",
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RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
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uart);
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}
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#endif
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#ifdef RT_USING_UART2
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{
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static struct rt_serial_device serial2;
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static struct jz_uart_s uart2;
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serial = &serial2;
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uart = &uart2;
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strcpy(uart->name, "uart2");
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#ifdef CONFIG_SYS_UART2_PD
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gpio_set_func(GPIO_PORT_D,GPIO_Pin_4,GPIO_FUNC_0);
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gpio_set_func(GPIO_PORT_D,GPIO_Pin_5,GPIO_FUNC_0);
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#else
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//USE JTAG IO for UART2
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gpio_set_func(GPIO_PORT_C,GPIO_Pin_31,GPIO_FUNC_1);
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#endif
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serial->ops = &_uart_ops;
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serial->config = config;
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serial->config.baud_rate = 115200;
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uart->hw_base = UART2_BASE;
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uart->irqno = IRQ_UART2;
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clk_enable(clk_get("uart2"));
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rt_hw_serial_register(serial,
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"uart2",
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RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
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uart);
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}
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#endif
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}
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/*
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* UART interface
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*/
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static rt_err_t uart_configure (struct rt_serial_device *serial, struct serial_configure *cfg)
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{
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rt_uint32_t baud_div;
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unsigned short *quot1;
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struct jz_uart_s * uart;
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RT_ASSERT(serial != RT_NULL);
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serial->config = *cfg;
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uart = serial->parent.user_data;
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RT_ASSERT(uart != RT_NULL);
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/* Init UART Hardware */
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UART_IER(uart->hw_base) = 0; /* clear interrupt */
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UART_FCR(uart->hw_base) = ~UARTFCR_UUE; /* disable UART unite */
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/* Enable UART clock */
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/* Set both receiver and transmitter in UART mode (not SIR) */
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UART_SIRCR(uart->hw_base) = ~(SIRCR_RSIRE | SIRCR_TSIRE);
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/* Set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
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UART_LCR(uart->hw_base) = UARTLCR_WLEN_8;
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/* set baudrate */
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quot1 = get_divisor(cfg->baud_rate);
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if (quot1 == RT_NULL)
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{
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#if defined(RT_USING_JZ4750) || defined(RT_USING_JZ4755) || defined(RT_USING_JZ4760)
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||
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if(REG_CPM_CPCCR & (1UL << 30))
|
||
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{
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||
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/* CPCCR.ECS = 1: clock source is EXCLK/2 */
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baud_div = BOARD_EXTAL_CLK / 2 / 16 / cfg->baud_rate;
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||
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}
|
||
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else
|
||
|
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#endif
|
||
|
|
{
|
||
|
|
/* CPCCR.ECS = 0: clock source is EXCLK */
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||
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baud_div = BOARD_EXTAL_CLK / 16 / cfg->baud_rate;
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||
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}
|
||
|
|
|
||
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UART_DLHR(uart->hw_base) = (baud_div >> 8) & 0xff;
|
||
|
|
UART_DLLR(uart->hw_base) = baud_div & 0xff;
|
||
|
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UART_LCR(uart->hw_base) &= ~UARTLCR_DLAB;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
UART_LCR(uart->hw_base) |= UARTLCR_DLAB;
|
||
|
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UART_DLHR(uart->hw_base) = (quot1[0] >> 8) & 0xff;
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||
|
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UART_DLLR(uart->hw_base) = quot1[0] & 0xff;
|
||
|
|
UART_LCR(uart->hw_base) &= ~UARTLCR_DLAB;
|
||
|
|
|
||
|
|
UART_UMR(uart->hw_base) = quot1[1] & 0xff;
|
||
|
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UART_UACR(uart->hw_base) = quot1[2] & 0xff;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (uart->hw_base == UART0_BASE)
|
||
|
|
{
|
||
|
|
rt_kprintf("enable uart0 CTS/RTS and hw flow control\n");
|
||
|
|
rt_kprintf("baudrate => %d\n", cfg->baud_rate);
|
||
|
|
|
||
|
|
rt_kprintf("div: %d, umr %d, uacr %d\n", quot1[0], quot1[1], quot1[2]);
|
||
|
|
|
||
|
|
/* configure CTS/RTS and hardware flow control */
|
||
|
|
UART_MCR(uart->hw_base) |= (UARTMCR_MCE | UARTMCR_FCM);
|
||
|
|
}
|
||
|
|
else if (uart->hw_base == UART1_BASE)
|
||
|
|
{
|
||
|
|
rt_kprintf("enable uart1 CTS/RTS and hw flow control\n");
|
||
|
|
rt_kprintf("baudrate => %d\n", cfg->baud_rate);
|
||
|
|
|
||
|
|
rt_kprintf("div: %d, umr %d, uacr %d\n", quot1[0], quot1[1], quot1[2]);
|
||
|
|
|
||
|
|
/* configure CTS/RTS and hardware flow control */
|
||
|
|
UART_MCR(uart->hw_base) |= (UARTMCR_MCE | UARTMCR_FCM);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Enable UART unit, enable and clear FIFO */
|
||
|
|
UART_FCR(uart->hw_base) = UARTFCR_UUE | UARTFCR_FE | UARTFCR_TFLS | UARTFCR_RFLS;
|
||
|
|
|
||
|
|
return (RT_EOK);
|
||
|
|
}
|
||
|
|
|
||
|
|
int uart_set_baudrate(int baudrate)
|
||
|
|
{
|
||
|
|
unsigned short *quot1;
|
||
|
|
struct jz_uart_s * uart;
|
||
|
|
struct rt_serial_device *serial;
|
||
|
|
|
||
|
|
serial = (struct rt_serial_device *)rt_device_find("uart0");
|
||
|
|
uart = serial->parent.user_data;
|
||
|
|
RT_ASSERT(uart != RT_NULL);
|
||
|
|
|
||
|
|
/* set baudrate */
|
||
|
|
quot1 = get_divisor(baudrate);
|
||
|
|
if (quot1)
|
||
|
|
{
|
||
|
|
UART_LCR(uart->hw_base) |= UARTLCR_DLAB;
|
||
|
|
UART_DLHR(uart->hw_base) = (quot1[0] >> 8) & 0xff;
|
||
|
|
UART_DLLR(uart->hw_base) = quot1[0] & 0xff;
|
||
|
|
UART_LCR(uart->hw_base) &= ~UARTLCR_DLAB;
|
||
|
|
|
||
|
|
UART_UMR(uart->hw_base) = quot1[1] & 0xff;
|
||
|
|
UART_UACR(uart->hw_base) = quot1[2] & 0xff;
|
||
|
|
}
|
||
|
|
|
||
|
|
rt_kprintf("change baudrate done!\n");
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static rt_err_t uart_control (struct rt_serial_device *serial, int cmd, void *arg)
|
||
|
|
{
|
||
|
|
struct jz_uart_s * uart;
|
||
|
|
|
||
|
|
uart = serial->parent.user_data;
|
||
|
|
|
||
|
|
RT_ASSERT(uart != RT_NULL);
|
||
|
|
|
||
|
|
switch (cmd)
|
||
|
|
{
|
||
|
|
case RT_DEVICE_CTRL_CLR_INT:
|
||
|
|
/* Disable the UART Interrupt */
|
||
|
|
UART_IER(uart->hw_base) &= ~(UARTIER_RIE | UARTIER_RTIE);
|
||
|
|
rt_hw_interrupt_mask(uart->irqno);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case RT_DEVICE_CTRL_SET_INT:
|
||
|
|
/* install interrupt */
|
||
|
|
rt_hw_interrupt_install(uart->irqno, uart_irq_handler,
|
||
|
|
serial, uart->name);
|
||
|
|
rt_hw_interrupt_umask(uart->irqno);
|
||
|
|
|
||
|
|
/* Enable the UART Interrupt */
|
||
|
|
UART_IER(uart->hw_base) |= (UARTIER_RIE | UARTIER_RTIE);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
return (RT_EOK);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int uart_putc (struct rt_serial_device *serial, char c)
|
||
|
|
{
|
||
|
|
struct jz_uart_s* uart;
|
||
|
|
int i = 0;
|
||
|
|
|
||
|
|
uart = serial->parent.user_data;
|
||
|
|
|
||
|
|
/* FIFO status, contain valid data */
|
||
|
|
while (!((UART_LSR(uart->hw_base) & (UARTLSR_TDRQ | UARTLSR_TEMT)) == 0x60))
|
||
|
|
{
|
||
|
|
i ++;
|
||
|
|
if (i > 0xfffff)
|
||
|
|
{
|
||
|
|
rt_kprintf("uart lst=>0x%02x\n", UART_LSR(uart->hw_base));
|
||
|
|
i = 0;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
/* write data */
|
||
|
|
UART_TDR(uart->hw_base) = c;
|
||
|
|
|
||
|
|
return (1);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int uart_getc (struct rt_serial_device *serial)
|
||
|
|
{
|
||
|
|
struct jz_uart_s* uart = serial->parent.user_data;
|
||
|
|
|
||
|
|
/* Receive Data Available */
|
||
|
|
if (UART_LSR(uart->hw_base) & UARTLSR_DR)
|
||
|
|
{
|
||
|
|
return UART_RDR(uart->hw_base);
|
||
|
|
}
|
||
|
|
|
||
|
|
return (-1);
|
||
|
|
}
|
||
|
|
|
||
|
|
static rt_size_t uart_dma_transmit (struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
|
||
|
|
{
|
||
|
|
return (0);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* UART interrupt handler */
|
||
|
|
static void uart_irq_handler(int irqno, void *param)
|
||
|
|
{
|
||
|
|
rt_ubase_t isr;
|
||
|
|
struct rt_serial_device *serial = (struct rt_serial_device*)param;
|
||
|
|
struct jz_uart_s* uart = serial->parent.user_data;
|
||
|
|
|
||
|
|
/* read interrupt status and clear it */
|
||
|
|
isr = UART_ISR(uart->hw_base);
|
||
|
|
if (isr & UARTISR_IID_RDI) /* Receive Data Available */
|
||
|
|
{
|
||
|
|
rt_hw_serial_isr(serial,RT_SERIAL_EVENT_RX_IND);
|
||
|
|
}
|
||
|
|
|
||
|
|
if(isr & UARTISR_IID_THRI)
|
||
|
|
{
|
||
|
|
rt_hw_serial_isr(serial,RT_SERIAL_EVENT_TX_DONE);
|
||
|
|
}
|
||
|
|
}
|