2015-02-05 19:27:24 +08:00
|
|
|
#ifndef USER_APP
|
2013-11-06 21:47:49 +08:00
|
|
|
#define USER_APP
|
|
|
|
/* ----------------------- Modbus includes ----------------------------------*/
|
|
|
|
#include "mb.h"
|
|
|
|
#include "mb_m.h"
|
|
|
|
#include "mbconfig.h"
|
|
|
|
#include "mbframe.h"
|
|
|
|
#include "mbutils.h"
|
|
|
|
|
|
|
|
/* -----------------------Slave Defines -------------------------------------*/
|
2015-02-05 19:27:24 +08:00
|
|
|
#define S_DISCRETE_INPUT_START 0
|
2013-11-06 21:47:49 +08:00
|
|
|
#define S_DISCRETE_INPUT_NDISCRETES 16
|
2015-02-05 19:27:24 +08:00
|
|
|
#define S_COIL_START 0
|
2013-11-06 21:47:49 +08:00
|
|
|
#define S_COIL_NCOILS 64
|
2015-02-05 19:27:24 +08:00
|
|
|
#define S_REG_INPUT_START 0
|
2013-11-06 21:47:49 +08:00
|
|
|
#define S_REG_INPUT_NREGS 100
|
2015-02-05 19:27:24 +08:00
|
|
|
#define S_REG_HOLDING_START 0
|
2013-11-06 21:47:49 +08:00
|
|
|
#define S_REG_HOLDING_NREGS 100
|
2015-02-05 19:27:24 +08:00
|
|
|
/* salve mode: holding register's all address */
|
|
|
|
#define S_HD_RESERVE 0
|
|
|
|
#define S_HD_CPU_USAGE_MAJOR 1
|
|
|
|
#define S_HD_CPU_USAGE_MINOR 2
|
|
|
|
/* salve mode: input register's all address */
|
|
|
|
#define S_IN_RESERVE 0
|
|
|
|
/* salve mode: coil's all address */
|
|
|
|
#define S_CO_RESERVE 0
|
|
|
|
/* salve mode: discrete's all address */
|
|
|
|
#define S_DI_RESERVE 0
|
2013-11-06 21:47:49 +08:00
|
|
|
|
|
|
|
/* -----------------------Master Defines -------------------------------------*/
|
2015-02-05 19:27:24 +08:00
|
|
|
#define M_DISCRETE_INPUT_START 0
|
2013-11-06 21:47:49 +08:00
|
|
|
#define M_DISCRETE_INPUT_NDISCRETES 16
|
2015-02-05 19:27:24 +08:00
|
|
|
#define M_COIL_START 0
|
2013-11-06 21:47:49 +08:00
|
|
|
#define M_COIL_NCOILS 64
|
2015-02-05 19:27:24 +08:00
|
|
|
#define M_REG_INPUT_START 0
|
2013-11-06 21:47:49 +08:00
|
|
|
#define M_REG_INPUT_NREGS 100
|
2015-02-05 19:27:24 +08:00
|
|
|
#define M_REG_HOLDING_START 0
|
2013-11-06 21:47:49 +08:00
|
|
|
#define M_REG_HOLDING_NREGS 100
|
2015-02-05 19:27:24 +08:00
|
|
|
/* master mode: holding register's all address */
|
|
|
|
#define M_HD_RESERVE 0
|
|
|
|
/* master mode: input register's all address */
|
|
|
|
#define M_IN_RESERVE 0
|
|
|
|
/* master mode: coil's all address */
|
|
|
|
#define M_CO_RESERVE 0
|
|
|
|
/* master mode: discrete's all address */
|
|
|
|
#define M_DI_RESERVE 0
|
2013-11-06 21:47:49 +08:00
|
|
|
|
|
|
|
#endif
|