225 lines
5.2 KiB
C
225 lines
5.2 KiB
C
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/*
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* File : drv_dma.h
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2015-11-19 Urey the first version
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*/
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#ifndef _DRV_DMA_H_
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#define _DRV_DMA_H_
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#include <stdint.h>
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#define NR_DMA_CHANNELS 8
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#define CH_DSA 0x00
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#define CH_DTA 0x04
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#define CH_DTC 0x08
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#define CH_DRT 0x0C
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#define CH_DCS 0x10
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#define CH_DCM 0x14
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#define CH_DDA 0x18
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#define CH_DSD 0x1C
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#define TCSM 0x2000
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#define DMAC 0x1000
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#define DIRQP 0x1004
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#define DESIRQP 0x1010
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#define DIC 0x1014
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#define DDR 0x1008
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#define DDRS 0x100C
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#define DMACP 0x101C
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#define DSIRQP 0x1020
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#define DSIRQM 0x1024
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#define DCIRQP 0x1028
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#define DCIRQM 0x102C
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/* MCU of PDMA */
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#define DMCS 0x1030
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#define DMNMB 0x1034
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#define DMSMB 0x1038
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#define DMINT 0x103C
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/* MCU of PDMA */
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#define DMINT_S_IP BIT(17)
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#define DMINT_N_IP BIT(16)
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#define DMAC_HLT BIT(3)
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#define DMAC_AR BIT(2)
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#define DCS_NDES BIT(31)
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#define DCS_AR BIT(4)
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#define DCS_TT BIT(3)
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#define DCS_HLT BIT(2)
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#define DCS_CTE BIT(0)
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#define DCM_SAI BIT(23)
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#define DCM_DAI BIT(22)
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#define DCM_SP_MSK (0x3 << 14)
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#define DCM_SP_32 DCM_SP_MSK
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#define DCM_SP_16 BIT(15)
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#define DCM_SP_8 BIT(14)
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#define DCM_DP_MSK (0x3 << 12)
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#define DCM_DP_32 DCM_DP_MSK
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#define DCM_DP_16 BIT(13)
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#define DCM_DP_8 BIT(12)
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#define DCM_TSZ_MSK (0x7 << 8)
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#define DCM_TSZ_SHF 8
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#define DCM_STDE BIT(2)
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#define DCM_TIE BIT(1)
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#define DCM_LINK BIT(0)
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#define DCM_CH1_SRC_TCSM (0x0 << 26)
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#define DCM_CH1_SRC_NEMC (0x1 << 26)
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#define DCM_CH1_SRC_DDR (0x2 << 26)
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#define DCM_CH1_DST_TCSM (0x0 << 24)
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#define DCM_CH1_DST_NEMC (0x1 << 24)
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#define DCM_CH1_DST_DDR (0x2 << 24)
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#define DCM_CH1_DDR_TO_NAND (DCM_CH1_SRC_DDR | DCM_CH1_DST_NEMC)
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#define DCM_CH1_NAND_TO_DDR (DCM_CH1_SRC_NEMC | DCM_CH1_DST_DDR)
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#define DCM_CH1_TCSM_TO_NAND (DCM_CH1_SRC_TCSM | DCM_CH1_DST_NEMC)
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#define DCM_CH1_NAND_TO_TCSM (DCM_CH1_SRC_NEMC | DCM_CH1_DST_TCSM)
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#define DCM_CH1_TCSM_TO_DDR (DCM_CH1_SRC_TCSM | DCM_CH1_DST_DDR)
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#define DCM_CH1_DDR_TO_TCSM (DCM_CH1_SRC_DDR | DCM_CH1_DST_TCSM)
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#define MCU_MSG_TYPE_NORMAL 0x1
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#define MCU_MSG_TYPE_INTC 0x2
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#define MCU_MSG_TYPE_INTC_MASKA 0x3
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enum jzdma_req_type {
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#define _RTP(NAME) JZDMA_REQ_##NAME##_TX,JZDMA_REQ_##NAME##_RX
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JZDMA_REQ_RESERVED0 = 0x03,
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_RTP(DMIC),
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_RTP(I2S0),
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JZDMA_REQ_AUTO_TXRX = 0x08,
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JZDMA_REQ_SADC_RX,
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JZDMA_REQ_RESERVED1 = 0x0b,
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_RTP(UART4),
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_RTP(UART3),
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_RTP(UART2),
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_RTP(UART1),
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_RTP(UART0),
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_RTP(SSI0),
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_RTP(SSI1),
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_RTP(MSC0),
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_RTP(MSC1),
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_RTP(MSC2),
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_RTP(PCM0),
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_RTP(PCM1),
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_RTP(I2C0),
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_RTP(I2C1),
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_RTP(I2C2),
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_RTP(I2C3),
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_RTP(I2C4),
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_RTP(DES),
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#undef _RTP
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};
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enum jzdma_type {
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JZDMA_REQ_INVAL = 0,
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#define _RTP(NAME) JZDMA_REQ_##NAME = JZDMA_REQ_##NAME##_TX
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_RTP(DMIC),
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_RTP(I2S0),
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JZDMA_REQ_AUTO = JZDMA_REQ_AUTO_TXRX,
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JZDMA_REQ_SADC = JZDMA_REQ_SADC_RX,
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_RTP(UART4),
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_RTP(UART3),
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_RTP(UART2),
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_RTP(UART1),
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_RTP(UART0),
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_RTP(SSI0),
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_RTP(SSI1),
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_RTP(MSC0),
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_RTP(MSC1),
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_RTP(MSC2),
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_RTP(PCM0),
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_RTP(PCM1),
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_RTP(I2C0),
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_RTP(I2C1),
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_RTP(I2C2),
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_RTP(I2C3),
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_RTP(I2C4),
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_RTP(DES),
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JZDMA_REQ_NAND0 = JZDMA_REQ_AUTO_TXRX | (1 << 16),
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JZDMA_REQ_NAND1 = JZDMA_REQ_AUTO_TXRX | (2 << 16),
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JZDMA_REQ_NAND2 = JZDMA_REQ_AUTO_TXRX | (3 << 16),
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JZDMA_REQ_NAND3 = JZDMA_REQ_AUTO_TXRX | (4 << 16),
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JZDMA_REQ_NAND4 = JZDMA_REQ_AUTO_TXRX | (5 << 16),
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TYPE_MASK = 0xffff,
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#undef _RTP
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};
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#define GET_MAP_TYPE(type) (type & (TYPE_MASK))
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enum channel_status
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{
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STAT_STOPED,STAT_SUBED,STAT_PREPED,STAT_RUNNING,
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};
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struct jzdma_desc
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{
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uint32_t dcm;
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uint32_t dsa;
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uint32_t dta;
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uint32_t dtc;
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uint32_t sd;
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uint32_t drt;
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uint32_t reserved[2];
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};
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struct jzdma_channel
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{
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// int id;
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uint32_t iomem;
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uint32_t dcs_saved;
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uint32_t dcm_def;
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enum jzdma_type type;
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enum channel_status status;
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//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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struct jzdma_desc desc;
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uint32_t desc_nr;
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// struct rt_dma_channel *parant;
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};
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struct jzdma_master
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{
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uint32_t base;
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struct clk *clk;
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int irq;
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int irq_pdmad; /* irq_pdmad for PDMA_DESC irq */
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struct jzdma_channel channel[NR_DMA_CHANNELS];
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};
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extern struct rt_dma_funcs _g_jzdma_funcs;
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#endif /* _DRV_DMA_H_ */
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