169 lines
4.5 KiB
C
169 lines
4.5 KiB
C
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/*
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* File : drv_slcdc.h
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* COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
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*
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* Change Logs:
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* Date Author Notes
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* 2017<EFBFBD><EFBFBD>3<EFBFBD><EFBFBD>21<EFBFBD><EFBFBD> Urey the first version
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*/
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#ifndef _DRV_SLCDC_H_
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#define _DRV_SLCDC_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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//#define CONFIG_SLCDC_CONTINUA
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#define SLCDC_USING_DUAL_BUFFER
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#define CONFIG_SLCDC_USE_TE
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#define FB_BASE 0x80200000
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#ifndef FB_PAGE_SIZE
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# define FB_PAGE_SIZE 4096
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#endif
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/* SLCDC reg ops */
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#define slcd_reg_write(addr,config) writel(config,addr)
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#define slcd_reg_read(addr) readl(addr)
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struct slcdc_dma_descriptor
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{
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uint32_t fdadr; /* Frame descriptor address register */
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uint32_t fsadr; /* Frame source address register */
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uint32_t fidr; /* Frame ID register */
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uint32_t ldcmd; /* Command register */
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uint32_t offsize; /* Stride Offsize(in word) */
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uint32_t page_width; /* Stride Pagewidth(in word) */
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uint32_t cmd_num; /* Command Number(for SLCD) */
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uint32_t desc_size; /* Foreground Size */
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};
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/* smart lcd interface_type */
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enum smart_lcd_type {
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SMART_LCD_TYPE_PARALLEL,
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SMART_LCD_TYPE_SERIAL,
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};
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/* smart lcd command width */
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enum smart_lcd_cwidth {
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SMART_LCD_CWIDTH_16_BIT_ONCE = (0 << 8),
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SMART_LCD_CWIDTH_9_BIT_ONCE = SMART_LCD_CWIDTH_16_BIT_ONCE,
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SMART_LCD_CWIDTH_8_BIT_ONCE = (0x1 << 8),
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SMART_LCD_CWIDTH_18_BIT_ONCE = (0x2 << 8),
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SMART_LCD_CWIDTH_24_BIT_ONCE = (0x3 << 8),
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};
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/* smart lcd data width */
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enum smart_lcd_dwidth {
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SMART_LCD_DWIDTH_18_BIT_ONCE_PARALLEL_SERIAL = (0 << 10),
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SMART_LCD_DWIDTH_16_BIT_ONCE_PARALLEL_SERIAL = (0x1 << 10),
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SMART_LCD_DWIDTH_8_BIT_THIRD_TIME_PARALLEL = (0x2 << 10),
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SMART_LCD_DWIDTH_8_BIT_TWICE_TIME_PARALLEL = (0x3 << 10),
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SMART_LCD_DWIDTH_8_BIT_ONCE_PARALLEL_SERIAL = (0x4 << 10),
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SMART_LCD_DWIDTH_24_BIT_ONCE_PARALLEL = (0x5 << 10),
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SMART_LCD_DWIDTH_9_BIT_TWICE_TIME_PARALLEL = (0x7 << 10),
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SMART_LCD_DWIDTH_MASK = (0x7 << 10),
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};
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/* smart lcd new data width */
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enum smart_lcd_new_dwidth {
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SMART_LCD_NEW_DWIDTH_24_BIT = (4 << 13),
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SMART_LCD_NEW_DWIDTH_18_BIT = (3 << 13),
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SMART_LCD_NEW_DWIDTH_16_BIT = (2 << 13),
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SMART_LCD_NEW_DWIDTH_9_BIT = (1 << 13),
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SMART_LCD_NEW_DWIDTH_8_BIT = (0 << 13),
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};
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/* smart lcd data times */
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enum smart_lcd_new_dtimes {
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SMART_LCD_NEW_DTIMES_ONCE = (0 << 8),
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SMART_LCD_NEW_DTIMES_TWICE = (1 << 8),
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SMART_LCD_NEW_DTIMES_THICE = (2 << 8),
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};
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/* smart lcd init code type */
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enum smart_config_type
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{
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SMART_CONFIG_CMD = 0,
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SMART_CONFIG_DATA = 1,
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SMART_CONFIG_UDELAY = 2,
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};
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struct slcd_data_table
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{
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enum smart_config_type type;
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uint32_t value;
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};
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typedef void (*lcd_bl_func_t)(rt_bool_t isPowerON);
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struct slcd_configure;
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struct slcdc_dev_s
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{
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struct rt_device parent;
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struct rt_mutex lock;
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struct slcd_configure *cfg;
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struct slcdc_dma_descriptor *desc_tmp;
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struct slcdc_dma_descriptor *desc_cmd;
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struct slcdc_dma_descriptor *desc_dat;
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struct slcdc_dma_descriptor *desc_self;
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rt_uint32_t fb_base;
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rt_uint32_t fb_cmd;
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rt_uint32_t fb_screen;
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#ifdef SLCDC_USING_DUAL_BUFFER
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rt_uint32_t fb_dual;
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#endif
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rt_uint32_t fb_size;
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};
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struct slcd_configure
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{
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unsigned pinmd :1;
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unsigned pixclk_falling_edge :1;
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unsigned data_enable_active_low :1;
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unsigned clkply_active_rising:1; /* smart lcd clock polarity:
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0: Active edge is Falling,
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1: Active edge is Rasing */
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unsigned rsply_cmd_high:1; /* smart lcd RS polarity.
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0: Command_RS=0, Data_RS=1;
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1: Command_RS=1, Data_RS=0 */
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unsigned csply_active_high:1; /* smart lcd CS Polarity.
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0: Active level is low,
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1: Active level is high */
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unsigned newcfg_6800_md:1;
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unsigned newcfg_fmt_conv:1;
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unsigned newcfg_cmd_9bit:1;
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rt_uint32_t width;
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rt_uint32_t height;
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rt_uint32_t fmt;
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rt_uint32_t bpp;
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rt_uint32_t bus_width;
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rt_uint32_t reg_width;
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rt_uint32_t refresh;
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const struct slcd_data_table *data_table;
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rt_uint32_t data_table_num;
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const rt_uint32_t *cmd_table; /* write GRAM command */
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rt_uint32_t cmd_table_num;
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};
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int rt_hw_slcd_init (struct slcd_configure *cfg);
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void rt_hw_slcd_set_bl_func (lcd_bl_func_t bl_func);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _DRV_SLCDC_H_ */
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