2014-06-29 00:34:20 +08:00
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/* K64F startup ARM GCC
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* Purpose: startup file for Cortex-M4 devices. Should use with
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* GCC for ARM Embedded Processors
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* Version: V1.2
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* Date: 15 Nov 2011
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*
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* Copyright (c) 2011, ARM Limited
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of the ARM Limited nor the
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names of its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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.syntax unified
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.arch armv7-m
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/* Memory Model
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The HEAP starts at the end of the DATA section and grows upward.
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The STACK starts at the end of the RAM and grows downward.
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The HEAP and stack STACK are only checked at compile time:
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(DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
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This is just a check for the bare minimum for the Heap+Stack area before
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aborting compilation, it is not the run time limit:
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Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
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*/
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.section .stack
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.align 3
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#ifdef __STACK_SIZE
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.equ Stack_Size, __STACK_SIZE
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#else
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.equ Stack_Size, 0xC00
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#endif
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.globl __StackTop
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.globl __StackLimit
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__StackLimit:
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.space Stack_Size
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.size __StackLimit, . - __StackLimit
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__StackTop:
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.size __StackTop, . - __StackTop
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.section .heap
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.align 3
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#ifdef __HEAP_SIZE
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.equ Heap_Size, __HEAP_SIZE
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#else
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.equ Heap_Size, 0x400
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#endif
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.globl __HeapBase
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.globl __HeapLimit
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__HeapBase:
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.space Heap_Size
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.size __HeapBase, . - __HeapBase
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__HeapLimit:
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.size __HeapLimit, . - __HeapLimit
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.section .vector_table,"a",%progbits
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.align 2
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.globl __isr_vector
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__isr_vector:
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.long __StackTop /* Top of Stack */
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.long Reset_Handler /* Reset Handler */
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.long NMI_Handler /* NMI Handler */
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.long HardFault_Handler /* Hard Fault Handler */
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.long MemManage_Handler /* MPU Fault Handler */
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.long BusFault_Handler /* Bus Fault Handler */
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.long UsageFault_Handler /* Usage Fault Handler */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long SVC_Handler /* SVCall Handler */
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.long DebugMon_Handler /* Debug Monitor Handler */
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.long 0 /* Reserved */
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.long PendSV_Handler /* PendSV Handler */
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.long SysTick_Handler /* SysTick Handler */
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/* External Interrupts */
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.long DMA0_IRQHandler /* DMA Channel 0 Transfer Complete */
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.long DMA1_IRQHandler /* DMA Channel 1 Transfer Complete */
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.long DMA2_IRQHandler /* DMA Channel 2 Transfer Complete */
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.long DMA3_IRQHandler /* DMA Channel 3 Transfer Complete */
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.long DMA4_IRQHandler /* DMA Channel 4 Transfer Complete */
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.long DMA5_IRQHandler /* DMA Channel 5 Transfer Complete */
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.long DMA6_IRQHandler /* DMA Channel 6 Transfer Complete */
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.long DMA7_IRQHandler /* DMA Channel 7 Transfer Complete */
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.long DMA8_IRQHandler /* DMA Channel 8 Transfer Complete */
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.long DMA9_IRQHandler /* DMA Channel 9 Transfer Complete */
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.long DMA10_IRQHandler /* DMA Channel 10 Transfer Complete */
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.long DMA11_IRQHandler /* DMA Channel 11 Transfer Complete */
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.long DMA12_IRQHandler /* DMA Channel 12 Transfer Complete */
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.long DMA13_IRQHandler /* DMA Channel 13 Transfer Complete */
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.long DMA14_IRQHandler /* DMA Channel 14 Transfer Complete */
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.long DMA15_IRQHandler /* DMA Channel 15 Transfer Complete */
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.long DMA_Error_IRQHandler /* DMA Error Interrupt */
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.long MCM_IRQHandler /* Normal Interrupt */
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.long FTFE_IRQHandler /* FTFE Command complete interrupt */
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.long Read_Collision_IRQHandler /* Read Collision Interrupt */
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.long LVD_LVW_IRQHandler /* Low Voltage Detect, Low Voltage Warning */
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.long LLW_IRQHandler /* Low Leakage Wakeup */
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.long Watchdog_IRQHandler /* WDOG Interrupt */
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.long RNG_IRQHandler /* RNG Interrupt */
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.long I2C0_IRQHandler /* I2C0 interrupt */
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.long I2C1_IRQHandler /* I2C1 interrupt */
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.long SPI0_IRQHandler /* SPI0 Interrupt */
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.long SPI1_IRQHandler /* SPI1 Interrupt */
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.long I2S0_Tx_IRQHandler /* I2S0 transmit interrupt */
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.long I2S0_Rx_IRQHandler /* I2S0 receive interrupt */
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.long UART0_LON_IRQHandler /* UART0 LON interrupt */
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.long UART0_RX_TX_IRQHandler /* UART0 Receive/Transmit interrupt */
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.long UART0_ERR_IRQHandler /* UART0 Error interrupt */
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.long UART1_RX_TX_IRQHandler /* UART1 Receive/Transmit interrupt */
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.long UART1_ERR_IRQHandler /* UART1 Error interrupt */
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.long UART2_RX_TX_IRQHandler /* UART2 Receive/Transmit interrupt */
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.long UART2_ERR_IRQHandler /* UART2 Error interrupt */
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.long UART3_RX_TX_IRQHandler /* UART3 Receive/Transmit interrupt */
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.long UART3_ERR_IRQHandler /* UART3 Error interrupt */
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.long ADC0_IRQHandler /* ADC0 interrupt */
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.long CMP0_IRQHandler /* CMP0 interrupt */
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.long CMP1_IRQHandler /* CMP1 interrupt */
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.long FTM0_IRQHandler /* FTM0 fault, overflow and channels interrupt */
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.long FTM1_IRQHandler /* FTM1 fault, overflow and channels interrupt */
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.long FTM2_IRQHandler /* FTM2 fault, overflow and channels interrupt */
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.long CMT_IRQHandler /* CMT interrupt */
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.long RTC_IRQHandler /* RTC interrupt */
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.long RTC_Seconds_IRQHandler /* RTC seconds interrupt */
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.long PIT0_IRQHandler /* PIT timer channel 0 interrupt */
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.long PIT1_IRQHandler /* PIT timer channel 1 interrupt */
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.long PIT2_IRQHandler /* PIT timer channel 2 interrupt */
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.long PIT3_IRQHandler /* PIT timer channel 3 interrupt */
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.long PDB0_IRQHandler /* PDB0 Interrupt */
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.long USB0_IRQHandler /* USB0 interrupt */
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.long USBDCD_IRQHandler /* USBDCD Interrupt */
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.long Reserved71_IRQHandler /* Reserved interrupt 71 */
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.long DAC0_IRQHandler /* DAC0 interrupt */
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.long MCG_IRQHandler /* MCG Interrupt */
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.long LPTimer_IRQHandler /* LPTimer interrupt */
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.long PORTA_IRQHandler /* Port A interrupt */
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.long PORTB_IRQHandler /* Port B interrupt */
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.long PORTC_IRQHandler /* Port C interrupt */
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.long PORTD_IRQHandler /* Port D interrupt */
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.long PORTE_IRQHandler /* Port E interrupt */
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.long SWI_IRQHandler /* Software interrupt */
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.long SPI2_IRQHandler /* SPI2 Interrupt */
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.long UART4_RX_TX_IRQHandler /* UART4 Receive/Transmit interrupt */
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.long UART4_ERR_IRQHandler /* UART4 Error interrupt */
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.long UART5_RX_TX_IRQHandler /* UART5 Receive/Transmit interrupt */
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.long UART5_ERR_IRQHandler /* UART5 Error interrupt */
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.long CMP2_IRQHandler /* CMP2 interrupt */
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.long FTM3_IRQHandler /* FTM3 fault, overflow and channels interrupt */
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.long DAC1_IRQHandler /* DAC1 interrupt */
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.long ADC1_IRQHandler /* ADC1 interrupt */
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.long I2C2_IRQHandler /* I2C2 interrupt */
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.long CAN0_ORed_Message_buffer_IRQHandler /* CAN0 OR'd message buffers interrupt */
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.long CAN0_Bus_Off_IRQHandler /* CAN0 bus off interrupt */
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.long CAN0_Error_IRQHandler /* CAN0 error interrupt */
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.long CAN0_Tx_Warning_IRQHandler /* CAN0 Tx warning interrupt */
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.long CAN0_Rx_Warning_IRQHandler /* CAN0 Rx warning interrupt */
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.long CAN0_Wake_Up_IRQHandler /* CAN0 wake up interrupt */
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.long SDHC_IRQHandler /* SDHC interrupt */
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.long ENET_1588_Timer_IRQHandler /* Ethernet MAC IEEE 1588 Timer Interrupt */
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.long ENET_Transmit_IRQHandler /* Ethernet MAC Transmit Interrupt */
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.long ENET_Receive_IRQHandler /* Ethernet MAC Receive Interrupt */
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.long ENET_Error_IRQHandler /* Ethernet MAC Error and miscelaneous Interrupt */
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.size __isr_vector, . - __isr_vector
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.section .text.Reset_Handler
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.thumb
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.thumb_func
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.align 2
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.globl Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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/* Loop to copy data from read only memory to RAM. The ranges
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* of copy from/to are specified by following symbols evaluated in
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* linker script.
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* __etext: End of code section, i.e., begin of data sections to copy from.
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* __data_start__/__data_end__: RAM address range that data should be
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* copied to. Both must be aligned to 4 bytes boundary. */
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disable_watchdog:
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/* unlock */
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ldr r1, =0x4005200e
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ldr r0, =0xc520
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strh r0, [r1]
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ldr r0, =0xd928
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strh r0, [r1]
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/* disable */
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ldr r1, =0x40052000
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ldr r0, =0x01d2
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strh r0, [r1]
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ldr r1, =__etext
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ldr r2, =__data_start__
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ldr r3, =__data_end__
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subs r3, r2
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ble .Lflash_to_ram_loop_end
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movs r4, 0
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.Lflash_to_ram_loop:
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ldr r0, [r1,r4]
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str r0, [r2,r4]
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adds r4, 4
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cmp r4, r3
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blt .Lflash_to_ram_loop
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.Lflash_to_ram_loop_end:
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ldr r0, =SystemInit
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blx r0
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2014-07-03 22:08:29 +08:00
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ldr r0, =init_data_bss
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blx r0
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ldr r0, =main
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2014-06-29 00:34:20 +08:00
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bx r0
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.pool
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.size Reset_Handler, . - Reset_Handler
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.text
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/* Macro to define default handlers. Default handler
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* will be weak symbol and just dead loops. They can be
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* overwritten by other handlers */
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.macro def_default_handler handler_name
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.align 1
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.thumb_func
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.weak \handler_name
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.type \handler_name, %function
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\handler_name :
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b .
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.size \handler_name, . - \handler_name
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.endm
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/* Exception Handlers */
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def_default_handler NMI_Handler
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def_default_handler HardFault_Handler
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def_default_handler MemManage_Handler
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def_default_handler BusFault_Handler
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def_default_handler UsageFault_Handler
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def_default_handler SVC_Handler
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def_default_handler DebugMon_Handler
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def_default_handler PendSV_Handler
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def_default_handler SysTick_Handler
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def_default_handler Default_Handler
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.macro def_irq_default_handler handler_name
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.weak \handler_name
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.set \handler_name, Default_Handler
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.endm
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/* IRQ Handlers */
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def_irq_default_handler DMA0_IRQHandler
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def_irq_default_handler DMA1_IRQHandler
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def_irq_default_handler DMA2_IRQHandler
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def_irq_default_handler DMA3_IRQHandler
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def_irq_default_handler DMA4_IRQHandler
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def_irq_default_handler DMA5_IRQHandler
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def_irq_default_handler DMA6_IRQHandler
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def_irq_default_handler DMA7_IRQHandler
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def_irq_default_handler DMA8_IRQHandler
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def_irq_default_handler DMA9_IRQHandler
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def_irq_default_handler DMA10_IRQHandler
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def_irq_default_handler DMA11_IRQHandler
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def_irq_default_handler DMA12_IRQHandler
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def_irq_default_handler DMA13_IRQHandler
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def_irq_default_handler DMA14_IRQHandler
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def_irq_default_handler DMA15_IRQHandler
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def_irq_default_handler DMA_Error_IRQHandler
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def_irq_default_handler MCM_IRQHandler
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def_irq_default_handler FTFE_IRQHandler
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def_irq_default_handler Read_Collision_IRQHandler
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def_irq_default_handler LVD_LVW_IRQHandler
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def_irq_default_handler LLW_IRQHandler
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def_irq_default_handler Watchdog_IRQHandler
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def_irq_default_handler RNG_IRQHandler
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def_irq_default_handler I2C0_IRQHandler
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def_irq_default_handler I2C1_IRQHandler
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def_irq_default_handler SPI0_IRQHandler
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def_irq_default_handler SPI1_IRQHandler
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def_irq_default_handler I2S0_Tx_IRQHandler
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def_irq_default_handler I2S0_Rx_IRQHandler
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def_irq_default_handler UART0_LON_IRQHandler
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def_irq_default_handler UART0_RX_TX_IRQHandler
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def_irq_default_handler UART0_ERR_IRQHandler
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def_irq_default_handler UART1_RX_TX_IRQHandler
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def_irq_default_handler UART1_ERR_IRQHandler
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def_irq_default_handler UART2_RX_TX_IRQHandler
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def_irq_default_handler UART2_ERR_IRQHandler
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def_irq_default_handler UART3_RX_TX_IRQHandler
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def_irq_default_handler UART3_ERR_IRQHandler
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def_irq_default_handler ADC0_IRQHandler
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def_irq_default_handler CMP0_IRQHandler
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def_irq_default_handler CMP1_IRQHandler
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def_irq_default_handler FTM0_IRQHandler
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def_irq_default_handler FTM1_IRQHandler
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def_irq_default_handler FTM2_IRQHandler
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def_irq_default_handler CMT_IRQHandler
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def_irq_default_handler RTC_IRQHandler
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def_irq_default_handler RTC_Seconds_IRQHandler
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def_irq_default_handler PIT0_IRQHandler
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def_irq_default_handler PIT1_IRQHandler
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def_irq_default_handler PIT2_IRQHandler
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def_irq_default_handler PIT3_IRQHandler
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def_irq_default_handler PDB0_IRQHandler
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def_irq_default_handler USB0_IRQHandler
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def_irq_default_handler USBDCD_IRQHandler
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def_irq_default_handler Reserved71_IRQHandler
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def_irq_default_handler DAC0_IRQHandler
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def_irq_default_handler MCG_IRQHandler
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def_irq_default_handler LPTimer_IRQHandler
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def_irq_default_handler PORTA_IRQHandler
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def_irq_default_handler PORTB_IRQHandler
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def_irq_default_handler PORTC_IRQHandler
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def_irq_default_handler PORTD_IRQHandler
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def_irq_default_handler PORTE_IRQHandler
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def_irq_default_handler SWI_IRQHandler
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def_irq_default_handler SPI2_IRQHandler
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def_irq_default_handler UART4_RX_TX_IRQHandler
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def_irq_default_handler UART4_ERR_IRQHandler
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def_irq_default_handler UART5_RX_TX_IRQHandler
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def_irq_default_handler UART5_ERR_IRQHandler
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def_irq_default_handler CMP2_IRQHandler
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def_irq_default_handler FTM3_IRQHandler
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def_irq_default_handler DAC1_IRQHandler
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def_irq_default_handler ADC1_IRQHandler
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def_irq_default_handler I2C2_IRQHandler
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def_irq_default_handler CAN0_ORed_Message_buffer_IRQHandler
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def_irq_default_handler CAN0_Bus_Off_IRQHandler
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def_irq_default_handler CAN0_Error_IRQHandler
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def_irq_default_handler CAN0_Tx_Warning_IRQHandler
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def_irq_default_handler CAN0_Rx_Warning_IRQHandler
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def_irq_default_handler CAN0_Wake_Up_IRQHandler
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def_irq_default_handler SDHC_IRQHandler
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def_irq_default_handler ENET_1588_Timer_IRQHandler
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def_irq_default_handler ENET_Transmit_IRQHandler
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def_irq_default_handler ENET_Receive_IRQHandler
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def_irq_default_handler ENET_Error_IRQHandler
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def_irq_default_handler DefaultISR
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/* Flash protection region, placed at 0x400 */
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.text
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.thumb
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.align 2
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.section .kinetis_flash_config_field,"a",%progbits
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kinetis_flash_config:
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.long 0xffffffff
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.long 0xffffffff
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.long 0xffffffff
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.long 0xfffffffe
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.end
|
