401 lines
12 KiB
C
401 lines
12 KiB
C
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/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_smc.h"
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#include "fsl_flash.h"
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#if (defined(FSL_FEATURE_SMC_HAS_PARAM) && FSL_FEATURE_SMC_HAS_PARAM)
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void SMC_GetParam(SMC_Type *base, smc_param_t *param)
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{
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uint32_t reg = base->PARAM;
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param->hsrunEnable = (bool)(reg & SMC_PARAM_EHSRUN_MASK);
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param->llsEnable = (bool)(reg & SMC_PARAM_ELLS_MASK);
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param->lls2Enable = (bool)(reg & SMC_PARAM_ELLS2_MASK);
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param->vlls0Enable = (bool)(reg & SMC_PARAM_EVLLS0_MASK);
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}
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#endif /* FSL_FEATURE_SMC_HAS_PARAM */
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void SMC_PreEnterStopModes(void)
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{
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flash_prefetch_speculation_status_t speculationStatus =
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{
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kFLASH_prefetchSpeculationOptionDisable, /* Disable instruction speculation.*/
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kFLASH_prefetchSpeculationOptionDisable, /* Disable data speculation.*/
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};
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__disable_irq();
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__ISB();
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/*
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* Before enter stop modes, the flash cache prefetch should be disabled.
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* Otherwise the prefetch might be interrupted by stop, then the data and
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* and instruction from flash are wrong.
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*/
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FLASH_PflashSetPrefetchSpeculation(&speculationStatus);
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}
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void SMC_PostExitStopModes(void)
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{
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flash_prefetch_speculation_status_t speculationStatus =
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{
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kFLASH_prefetchSpeculationOptionEnable, /* Enable instruction speculation.*/
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kFLASH_prefetchSpeculationOptionEnable, /* Enable data speculation.*/
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};
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FLASH_PflashSetPrefetchSpeculation(&speculationStatus);
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__enable_irq();
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__ISB();
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}
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status_t SMC_SetPowerModeRun(SMC_Type *base)
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{
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uint8_t reg;
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reg = base->PMCTRL;
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/* configure Normal RUN mode */
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reg &= ~SMC_PMCTRL_RUNM_MASK;
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reg |= (kSMC_RunNormal << SMC_PMCTRL_RUNM_SHIFT);
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base->PMCTRL = reg;
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return kStatus_Success;
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}
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#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE)
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status_t SMC_SetPowerModeHsrun(SMC_Type *base)
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{
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uint8_t reg;
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reg = base->PMCTRL;
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/* configure High Speed RUN mode */
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reg &= ~SMC_PMCTRL_RUNM_MASK;
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reg |= (kSMC_Hsrun << SMC_PMCTRL_RUNM_SHIFT);
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base->PMCTRL = reg;
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return kStatus_Success;
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}
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#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */
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status_t SMC_SetPowerModeWait(SMC_Type *base)
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{
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/* configure Normal Wait mode */
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SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
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__DSB();
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__WFI();
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__ISB();
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return kStatus_Success;
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}
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status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option)
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{
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uint8_t reg;
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#if (defined(FSL_FEATURE_SMC_HAS_PSTOPO) && FSL_FEATURE_SMC_HAS_PSTOPO)
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/* configure the Partial Stop mode in Noraml Stop mode */
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reg = base->STOPCTRL;
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reg &= ~SMC_STOPCTRL_PSTOPO_MASK;
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reg |= ((uint32_t)option << SMC_STOPCTRL_PSTOPO_SHIFT);
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base->STOPCTRL = reg;
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#endif
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/* configure Normal Stop mode */
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reg = base->PMCTRL;
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reg &= ~SMC_PMCTRL_STOPM_MASK;
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reg |= (kSMC_StopNormal << SMC_PMCTRL_STOPM_SHIFT);
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base->PMCTRL = reg;
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/* Set the SLEEPDEEP bit to enable deep sleep mode (stop mode) */
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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/* read back to make sure the configuration valid before enter stop mode */
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(void)base->PMCTRL;
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__DSB();
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__WFI();
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__ISB();
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/* check whether the power mode enter Stop mode succeed */
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if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
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{
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return kStatus_SMC_StopAbort;
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}
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else
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{
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return kStatus_Success;
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}
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}
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status_t SMC_SetPowerModeVlpr(SMC_Type *base
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#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
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,
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bool wakeupMode
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#endif
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)
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{
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uint8_t reg;
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reg = base->PMCTRL;
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#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
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/* configure whether the system remains in VLP mode on an interrupt */
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if (wakeupMode)
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{
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/* exits to RUN mode on an interrupt */
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reg |= SMC_PMCTRL_LPWUI_MASK;
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}
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else
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{
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/* remains in VLP mode on an interrupt */
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reg &= ~SMC_PMCTRL_LPWUI_MASK;
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}
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#endif /* FSL_FEATURE_SMC_HAS_LPWUI */
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/* configure VLPR mode */
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reg &= ~SMC_PMCTRL_RUNM_MASK;
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reg |= (kSMC_RunVlpr << SMC_PMCTRL_RUNM_SHIFT);
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base->PMCTRL = reg;
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return kStatus_Success;
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}
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status_t SMC_SetPowerModeVlpw(SMC_Type *base)
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{
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/* configure VLPW mode */
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/* Set the SLEEPDEEP bit to enable deep sleep mode */
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SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
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__DSB();
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__WFI();
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__ISB();
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return kStatus_Success;
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}
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status_t SMC_SetPowerModeVlps(SMC_Type *base)
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{
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uint8_t reg;
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/* configure VLPS mode */
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reg = base->PMCTRL;
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reg &= ~SMC_PMCTRL_STOPM_MASK;
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reg |= (kSMC_StopVlps << SMC_PMCTRL_STOPM_SHIFT);
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base->PMCTRL = reg;
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/* Set the SLEEPDEEP bit to enable deep sleep mode */
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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/* read back to make sure the configuration valid before enter stop mode */
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(void)base->PMCTRL;
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__DSB();
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__WFI();
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__ISB();
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/* check whether the power mode enter VLPS mode succeed */
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if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
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{
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return kStatus_SMC_StopAbort;
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}
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else
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{
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return kStatus_Success;
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}
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}
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#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE)
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status_t SMC_SetPowerModeLls(SMC_Type *base
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#if ((defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) || \
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(defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO))
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,
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const smc_power_mode_lls_config_t *config
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#endif
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)
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{
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uint8_t reg;
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/* configure to LLS mode */
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reg = base->PMCTRL;
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reg &= ~SMC_PMCTRL_STOPM_MASK;
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reg |= (kSMC_StopLls << SMC_PMCTRL_STOPM_SHIFT);
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base->PMCTRL = reg;
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/* configure LLS sub-mode*/
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#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE)
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reg = base->STOPCTRL;
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reg &= ~SMC_STOPCTRL_LLSM_MASK;
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reg |= ((uint32_t)config->subMode << SMC_STOPCTRL_LLSM_SHIFT);
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base->STOPCTRL = reg;
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#endif /* FSL_FEATURE_SMC_HAS_LLS_SUBMODE */
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#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)
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if (config->enableLpoClock)
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{
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base->STOPCTRL &= ~SMC_STOPCTRL_LPOPO_MASK;
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}
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else
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{
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base->STOPCTRL |= SMC_STOPCTRL_LPOPO_MASK;
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}
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#endif /* FSL_FEATURE_SMC_HAS_LPOPO */
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/* Set the SLEEPDEEP bit to enable deep sleep mode */
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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/* read back to make sure the configuration valid before enter stop mode */
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(void)base->PMCTRL;
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__DSB();
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__WFI();
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__ISB();
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/* check whether the power mode enter LLS mode succeed */
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if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
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{
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return kStatus_SMC_StopAbort;
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}
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else
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{
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return kStatus_Success;
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}
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}
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#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */
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#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE)
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status_t SMC_SetPowerModeVlls(SMC_Type *base, const smc_power_mode_vlls_config_t *config)
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{
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uint8_t reg;
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#if (defined(FSL_FEATURE_SMC_HAS_PORPO) && FSL_FEATURE_SMC_HAS_PORPO)
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#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) || \
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(defined(FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) && FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) || \
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(defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE)
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if (config->subMode == kSMC_StopSub0)
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#endif
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{
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/* configure whether the Por Detect work in Vlls0 mode */
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if (config->enablePorDetectInVlls0)
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{
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#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG)
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base->VLLSCTRL &= ~SMC_VLLSCTRL_PORPO_MASK;
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#else
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base->STOPCTRL &= ~SMC_STOPCTRL_PORPO_MASK;
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#endif
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}
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else
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{
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#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG)
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base->VLLSCTRL |= SMC_VLLSCTRL_PORPO_MASK;
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#else
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base->STOPCTRL |= SMC_STOPCTRL_PORPO_MASK;
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#endif
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}
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}
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#endif /* FSL_FEATURE_SMC_HAS_PORPO */
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#if (defined(FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) && FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION)
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else if (config->subMode == kSMC_StopSub2)
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{
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/* configure whether the Por Detect work in Vlls0 mode */
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if (config->enableRam2InVlls2)
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{
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#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG)
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base->VLLSCTRL |= SMC_VLLSCTRL_RAM2PO_MASK;
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#else
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base->STOPCTRL |= SMC_STOPCTRL_RAM2PO_MASK;
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#endif
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}
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else
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{
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#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG)
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base->VLLSCTRL &= ~SMC_VLLSCTRL_RAM2PO_MASK;
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#else
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base->STOPCTRL &= ~SMC_STOPCTRL_RAM2PO_MASK;
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#endif
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}
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}
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else
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{
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}
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#endif /* FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION */
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/* configure to VLLS mode */
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reg = base->PMCTRL;
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reg &= ~SMC_PMCTRL_STOPM_MASK;
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reg |= (kSMC_StopVlls << SMC_PMCTRL_STOPM_SHIFT);
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base->PMCTRL = reg;
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/* configure the VLLS sub-mode */
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#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG)
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||
|
|
reg = base->VLLSCTRL;
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||
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|
reg &= ~SMC_VLLSCTRL_VLLSM_MASK;
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||
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|
reg |= ((uint32_t)config->subMode << SMC_VLLSCTRL_VLLSM_SHIFT);
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||
|
|
base->VLLSCTRL = reg;
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||
|
|
#else
|
||
|
|
#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE)
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||
|
|
reg = base->STOPCTRL;
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||
|
|
reg &= ~SMC_STOPCTRL_LLSM_MASK;
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||
|
|
reg |= ((uint32_t)config->subMode << SMC_STOPCTRL_LLSM_SHIFT);
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||
|
|
base->STOPCTRL = reg;
|
||
|
|
#else
|
||
|
|
reg = base->STOPCTRL;
|
||
|
|
reg &= ~SMC_STOPCTRL_VLLSM_MASK;
|
||
|
|
reg |= ((uint32_t)config->subMode << SMC_STOPCTRL_VLLSM_SHIFT);
|
||
|
|
base->STOPCTRL = reg;
|
||
|
|
#endif /* FSL_FEATURE_SMC_HAS_LLS_SUBMODE */
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)
|
||
|
|
if (config->enableLpoClock)
|
||
|
|
{
|
||
|
|
base->STOPCTRL &= ~SMC_STOPCTRL_LPOPO_MASK;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
base->STOPCTRL |= SMC_STOPCTRL_LPOPO_MASK;
|
||
|
|
}
|
||
|
|
#endif /* FSL_FEATURE_SMC_HAS_LPOPO */
|
||
|
|
|
||
|
|
/* Set the SLEEPDEEP bit to enable deep sleep mode */
|
||
|
|
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||
|
|
|
||
|
|
/* read back to make sure the configuration valid before enter stop mode */
|
||
|
|
(void)base->PMCTRL;
|
||
|
|
__DSB();
|
||
|
|
__WFI();
|
||
|
|
__ISB();
|
||
|
|
|
||
|
|
/* check whether the power mode enter LLS mode succeed */
|
||
|
|
if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
|
||
|
|
{
|
||
|
|
return kStatus_SMC_StopAbort;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
return kStatus_Success;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#endif /* FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE */
|