288 lines
9.0 KiB
C
288 lines
9.0 KiB
C
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/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_rnga.h"
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#if defined(FSL_FEATURE_SOC_RNG_COUNT) && FSL_FEATURE_SOC_RNG_COUNT
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/*******************************************************************************
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* Definitions
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*******************************************************************************/
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/*******************************************************************************
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* RNG_CR - RNGA Control Register
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******************************************************************************/
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/*!
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* @brief RNG_CR - RNGA Control Register (RW)
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*
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* Reset value: 0x00000000U
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*
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* Controls the operation of RNGA.
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*/
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/*!
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* @name Constants and macros for entire RNG_CR register
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*/
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/*@{*/
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#define RNG_CR_REG(base) ((base)->CR)
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#define RNG_RD_CR(base) (RNG_CR_REG(base))
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#define RNG_WR_CR(base, value) (RNG_CR_REG(base) = (value))
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#define RNG_RMW_CR(base, mask, value) (RNG_WR_CR(base, (RNG_RD_CR(base) & ~(mask)) | (value)))
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/*@}*/
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/*!
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* @name Register RNG_CR, field GO[0] (RW)
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*
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* Specifies whether random-data generation and loading (into OR[RANDOUT]) is
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* enabled.This field is sticky. You must reset RNGA to stop RNGA from loading
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* OR[RANDOUT] with data.
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*
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* Values:
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* - 0b0 - Disabled
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* - 0b1 - Enabled
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*/
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/*@{*/
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/*! @brief Read current value of the RNG_CR_GO field. */
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#define RNG_RD_CR_GO(base) ((RNG_CR_REG(base) & RNG_CR_GO_MASK) >> RNG_CR_GO_SHIFT)
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/*! @brief Set the GO field to a new value. */
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#define RNG_WR_CR_GO(base, value) (RNG_RMW_CR(base, RNG_CR_GO_MASK, RNG_CR_GO(value)))
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/*@}*/
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/*!
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* @name Register RNG_CR, field SLP[4] (RW)
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*
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* Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
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* mode by asserting the DOZE signal.
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*
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* Values:
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* - 0b0 - Normal mode
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* - 0b1 - Sleep (low-power) mode
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*/
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/*@{*/
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/*! @brief Read current value of the RNG_CR_SLP field. */
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#define RNG_RD_CR_SLP(base) ((RNG_CR_REG(base) & RNG_CR_SLP_MASK) >> RNG_CR_SLP_SHIFT)
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/*! @brief Set the SLP field to a new value. */
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#define RNG_WR_CR_SLP(base, value) (RNG_RMW_CR(base, RNG_CR_SLP_MASK, RNG_CR_SLP(value)))
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/*@}*/
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/*******************************************************************************
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* RNG_SR - RNGA Status Register
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******************************************************************************/
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#define RNG_SR_REG(base) ((base)->SR)
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/*!
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* @name Register RNG_SR, field OREG_LVL[15:8] (RO)
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*
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* Indicates the number of random-data words that are in OR[RANDOUT], which
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* indicates whether OR[RANDOUT] is valid.If you read OR[RANDOUT] when SR[OREG_LVL]
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* is not 0, then the contents of a random number contained in OR[RANDOUT] are
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* returned, and RNGA writes 0 to both OR[RANDOUT] and SR[OREG_LVL].
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*
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* Values:
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* - 0b00000000 - No words (empty)
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* - 0b00000001 - One word (valid)
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*/
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/*@{*/
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/*! @brief Read current value of the RNG_SR_OREG_LVL field. */
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#define RNG_RD_SR_OREG_LVL(base) ((RNG_SR_REG(base) & RNG_SR_OREG_LVL_MASK) >> RNG_SR_OREG_LVL_SHIFT)
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/*@}*/
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/*!
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* @name Register RNG_SR, field SLP[4] (RO)
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*
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* Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
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* mode by asserting the DOZE signal.
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*
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* Values:
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* - 0b0 - Normal mode
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* - 0b1 - Sleep (low-power) mode
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*/
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/*@{*/
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/*! @brief Read current value of the RNG_SR_SLP field. */
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#define RNG_RD_SR_SLP(base) ((RNG_SR_REG(base) & RNG_SR_SLP_MASK) >> RNG_SR_SLP_SHIFT)
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/*@}*/
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/*******************************************************************************
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* RNG_OR - RNGA Output Register
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******************************************************************************/
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/*!
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* @brief RNG_OR - RNGA Output Register (RO)
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*
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* Reset value: 0x00000000U
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*
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* Stores a random-data word generated by RNGA.
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*/
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/*!
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* @name Constants and macros for entire RNG_OR register
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*/
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/*@{*/
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#define RNG_OR_REG(base) ((base)->OR)
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#define RNG_RD_OR(base) (RNG_OR_REG(base))
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/*@}*/
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/*******************************************************************************
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* RNG_ER - RNGA Entropy Register
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******************************************************************************/
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/*!
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* @brief RNG_ER - RNGA Entropy Register (WORZ)
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*
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* Reset value: 0x00000000U
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*
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* Specifies an entropy value that RNGA uses in addition to its ring oscillators
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* to seed its pseudorandom algorithm. This is a write-only register; reads
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* return all zeros.
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*/
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/*!
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* @name Constants and macros for entire RNG_ER register
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*/
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/*@{*/
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#define RNG_ER_REG(base) ((base)->ER)
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#define RNG_RD_ER(base) (RNG_ER_REG(base))
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#define RNG_WR_ER(base, value) (RNG_ER_REG(base) = (value))
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/*@}*/
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/*******************************************************************************
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* Prototypes
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*******************************************************************************/
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static uint32_t rnga_ReadEntropy(RNG_Type *base);
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/*******************************************************************************
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* Code
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******************************************************************************/
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void RNGA_Init(RNG_Type *base)
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{
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Enable the clock gate. */
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CLOCK_EnableClock(kCLOCK_Rnga0);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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CLOCK_DisableClock(kCLOCK_Rnga0); /* To solve the release version on twrkm43z75m */
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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CLOCK_EnableClock(kCLOCK_Rnga0);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/* Reset the registers for RNGA module to reset state. */
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RNG_WR_CR(base, 0);
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/* Enables the RNGA random data generation and loading.*/
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RNG_WR_CR_GO(base, 1);
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}
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void RNGA_Deinit(RNG_Type *base)
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{
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Disable the clock for RNGA module.*/
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CLOCK_DisableClock(kCLOCK_Rnga0);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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/*!
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* @brief Get a random data from RNGA.
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*
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* @param base RNGA base address
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*/
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static uint32_t rnga_ReadEntropy(RNG_Type *base)
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{
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uint32_t data = 0;
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if (RNGA_GetMode(base) == kRNGA_ModeNormal) /* Is in normal mode.*/
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{
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/* Wait for valid random-data.*/
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while (RNG_RD_SR_OREG_LVL(base) == 0)
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{
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}
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data = RNG_RD_OR(base);
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}
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/* Get random-data word generated by RNGA.*/
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return data;
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}
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status_t RNGA_GetRandomData(RNG_Type *base, void *data, size_t data_size)
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{
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status_t result = kStatus_Success;
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uint32_t random_32;
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uint8_t *random_p;
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uint32_t random_size;
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uint8_t *data_p = (uint8_t *)data;
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uint32_t i;
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/* Check input parameters.*/
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if (base && data && data_size)
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{
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do
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{
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/* Read Entropy.*/
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random_32 = rnga_ReadEntropy(base);
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random_p = (uint8_t *)&random_32;
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if (data_size < sizeof(random_32))
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{
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random_size = data_size;
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}
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else
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{
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random_size = sizeof(random_32);
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}
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for (i = 0; i < random_size; i++)
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{
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*data_p++ = *random_p++;
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}
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data_size -= random_size;
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} while (data_size > 0);
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}
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else
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{
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result = kStatus_InvalidArgument;
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}
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return result;
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}
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void RNGA_SetMode(RNG_Type *base, rnga_mode_t mode)
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{
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RNG_WR_CR_SLP(base, (uint32_t)mode);
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}
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rnga_mode_t RNGA_GetMode(RNG_Type *base)
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{
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return (rnga_mode_t)RNG_RD_SR_SLP(base);
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}
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void RNGA_Seed(RNG_Type *base, uint32_t seed)
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{
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/* Write to RNGA Entropy Register.*/
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RNG_WR_ER(base, seed);
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}
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#endif /* FSL_FEATURE_SOC_RNG_COUNT */
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