2011-06-23 08:47:34 +08:00
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//*****************************************************************************
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//
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// hw_ints.h - Macros that define the interrupt assignment on Stellaris.
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//
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2011-12-23 10:59:07 +08:00
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// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
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2011-06-23 08:47:34 +08:00
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// Software License Agreement
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//
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// Texas Instruments (TI) is supplying this software for use solely and
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// exclusively on TI's microcontroller products. The software is owned by
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// TI and/or its suppliers, and is protected under applicable copyright
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// laws. You may not combine this software with "viral" open-source
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// software in order to form a larger program.
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//
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// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
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// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
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// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
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// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
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// DAMAGES, FOR ANY REASON WHATSOEVER.
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//
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2011-12-23 10:59:07 +08:00
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// This is part of revision 8264 of the Stellaris Firmware Development Package.
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2011-06-23 08:47:34 +08:00
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//
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//*****************************************************************************
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#ifndef __HW_INTS_H__
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#define __HW_INTS_H__
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//*****************************************************************************
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//
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// The following are defines for the fault assignments.
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//
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//*****************************************************************************
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#define FAULT_NMI 2 // NMI fault
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#define FAULT_HARD 3 // Hard fault
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#define FAULT_MPU 4 // MPU fault
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#define FAULT_BUS 5 // Bus fault
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#define FAULT_USAGE 6 // Usage fault
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#define FAULT_SVCALL 11 // SVCall
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#define FAULT_DEBUG 12 // Debug monitor
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#define FAULT_PENDSV 14 // PendSV
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#define FAULT_SYSTICK 15 // System Tick
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//*****************************************************************************
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//
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// The following are defines for the interrupt assignments.
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//
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//*****************************************************************************
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#define INT_GPIOA 16 // GPIO Port A
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#define INT_GPIOB 17 // GPIO Port B
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#define INT_GPIOC 18 // GPIO Port C
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#define INT_GPIOD 19 // GPIO Port D
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#define INT_GPIOE 20 // GPIO Port E
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#define INT_UART0 21 // UART0 Rx and Tx
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#define INT_UART1 22 // UART1 Rx and Tx
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#define INT_SSI0 23 // SSI0 Rx and Tx
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#define INT_I2C0 24 // I2C0 Master and Slave
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2011-12-23 10:59:07 +08:00
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#define INT_PWM0_FAULT 25 // PWM0 Fault
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#define INT_PWM0_0 26 // PWM0 Generator 0
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#define INT_PWM0_1 27 // PWM0 Generator 1
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#define INT_PWM0_2 28 // PWM0 Generator 2
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#define INT_QEI0 29 // Quadrature Encoder 0
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#define INT_ADC0SS0 30 // ADC0 Sequence 0
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#define INT_ADC0SS1 31 // ADC0 Sequence 1
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#define INT_ADC0SS2 32 // ADC0 Sequence 2
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#define INT_ADC0SS3 33 // ADC0 Sequence 3
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#define INT_WATCHDOG 34 // Watchdog timer
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#define INT_TIMER0A 35 // Timer 0 subtimer A
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#define INT_TIMER0B 36 // Timer 0 subtimer B
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#define INT_TIMER1A 37 // Timer 1 subtimer A
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#define INT_TIMER1B 38 // Timer 1 subtimer B
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#define INT_TIMER2A 39 // Timer 2 subtimer A
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#define INT_TIMER2B 40 // Timer 2 subtimer B
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#define INT_COMP0 41 // Analog Comparator 0
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#define INT_COMP1 42 // Analog Comparator 1
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#define INT_COMP2 43 // Analog Comparator 2
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#define INT_SYSCTL 44 // System Control (PLL, OSC, BO)
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#define INT_FLASH 45 // FLASH Control
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#define INT_GPIOF 46 // GPIO Port F
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#define INT_GPIOG 47 // GPIO Port G
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#define INT_GPIOH 48 // GPIO Port H
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#define INT_UART2 49 // UART2 Rx and Tx
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#define INT_SSI1 50 // SSI1 Rx and Tx
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#define INT_TIMER3A 51 // Timer 3 subtimer A
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#define INT_TIMER3B 52 // Timer 3 subtimer B
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#define INT_I2C1 53 // I2C1 Master and Slave
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#define INT_QEI1 54 // Quadrature Encoder 1
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#define INT_CAN0 55 // CAN0
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#define INT_CAN1 56 // CAN1
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#define INT_CAN2 57 // CAN2
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#define INT_ETH 58 // Ethernet
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#define INT_HIBERNATE 59 // Hibernation module
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#define INT_USB0 60 // USB 0 Controller
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#define INT_PWM0_3 61 // PWM0 Generator 3
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#define INT_UDMA 62 // uDMA controller
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#define INT_UDMAERR 63 // uDMA Error
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#define INT_ADC1SS0 64 // ADC1 Sequence 0
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#define INT_ADC1SS1 65 // ADC1 Sequence 1
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#define INT_ADC1SS2 66 // ADC1 Sequence 2
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#define INT_ADC1SS3 67 // ADC1 Sequence 3
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#define INT_I2S0 68 // I2S0
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#define INT_EPI0 69 // EPI0
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#define INT_GPIOJ 70 // GPIO Port J
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#define INT_GPIOK 71 // GPIO Port K
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#define INT_GPIOL 72 // GPIO Port L
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#define INT_SSI2 73 // SSI2
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#define INT_SSI3 74 // SSI3
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#define INT_UART3 75 // UART3
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#define INT_UART4 76 // UART4
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#define INT_UART5 77 // UART5
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#define INT_UART6 78 // UART6
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#define INT_UART7 79 // UART7
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#define INT_I2C2 84 // I2C2
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#define INT_I2C3 85 // I2C3
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#define INT_TIMER4A 86 // Timer 4A
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#define INT_TIMER4B 87 // Timer 4B
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#define INT_TIMER5A 108 // Timer 5A
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#define INT_TIMER5B 109 // Timer 5B
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#define INT_WTIMER0A 110 // Wide Timer 0A
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#define INT_WTIMER0B 111 // Wide Timer 0B
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#define INT_WTIMER1A 112 // Wide Timer 1A
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#define INT_WTIMER1B 113 // Wide Timer 1B
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#define INT_WTIMER2A 114 // Wide Timer 2A
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#define INT_WTIMER2B 115 // Wide Timer 2B
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#define INT_WTIMER3A 116 // Wide Timer 3A
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#define INT_WTIMER3B 117 // Wide Timer 3B
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#define INT_WTIMER4A 118 // Wide Timer 4A
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#define INT_WTIMER4B 119 // Wide Timer 4B
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#define INT_WTIMER5A 120 // Wide Timer 5A
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#define INT_WTIMER5B 121 // Wide Timer 5B
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#define INT_SYSEXC 122 // System Exception (imprecise)
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#define INT_PECI0 123 // PECI 0
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#define INT_LPC0 124 // LPC 0
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#define INT_I2C4 125 // I2C4
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#define INT_I2C5 126 // I2C5
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#define INT_GPIOM 127 // GPIO Port M
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#define INT_GPION 128 // GPIO Port N
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#define INT_FAN0 130 // FAN 0
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#define INT_GPIOP0 132 // GPIO Port P (Summary or P0)
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#define INT_GPIOP1 133 // GPIO Port P1
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#define INT_GPIOP2 134 // GPIO Port P2
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#define INT_GPIOP3 135 // GPIO Port P3
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#define INT_GPIOP4 136 // GPIO Port P4
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#define INT_GPIOP5 137 // GPIO Port P5
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#define INT_GPIOP6 138 // GPIO Port P6
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#define INT_GPIOP7 139 // GPIO Port P7
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#define INT_GPIOQ0 140 // GPIO Port Q (Summary or Q0)
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#define INT_GPIOQ1 141 // GPIO Port Q1
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#define INT_GPIOQ2 142 // GPIO Port Q2
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#define INT_GPIOQ3 143 // GPIO Port Q3
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#define INT_GPIOQ4 144 // GPIO Port Q4
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#define INT_GPIOQ5 145 // GPIO Port Q5
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#define INT_GPIOQ6 146 // GPIO Port Q6
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#define INT_GPIOQ7 147 // GPIO Port Q7
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#define INT_PWM1_0 150 // PWM1 Generator 0
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#define INT_PWM1_1 151 // PWM1 Generator 1
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#define INT_PWM1_2 152 // PWM1 Generator 2
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#define INT_PWM1_3 153 // PWM1 Generator 3
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#define INT_PWM1_FAULT 154 // PWM1 Fault
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2011-06-23 08:47:34 +08:00
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//*****************************************************************************
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//
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// The following are defines for the total number of interrupts.
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//
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//*****************************************************************************
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2011-12-23 10:59:07 +08:00
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#define NUM_INTERRUPTS 155
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2011-06-23 08:47:34 +08:00
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//*****************************************************************************
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//
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// The following are defines for the total number of priority levels.
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//
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//*****************************************************************************
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#define NUM_PRIORITY 8
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#define NUM_PRIORITY_BITS 3
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//*****************************************************************************
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//
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// The following definitions are deprecated.
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//
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//*****************************************************************************
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#ifndef DEPRECATED
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//*****************************************************************************
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//
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// The following are deprecated defines for the interrupt assignments.
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//
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//*****************************************************************************
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#define INT_SSI 23 // SSI Rx and Tx
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#define INT_I2C 24 // I2C Master and Slave
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#define INT_PWM_FAULT 25 // PWM Fault
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#define INT_PWM0 26 // PWM Generator 0
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#define INT_PWM1 27 // PWM Generator 1
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#define INT_PWM2 28 // PWM Generator 2
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#define INT_QEI 29 // Quadrature Encoder
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#define INT_ADC0 30 // ADC Sequence 0
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#define INT_ADC1 31 // ADC Sequence 1
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#define INT_ADC2 32 // ADC Sequence 2
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#define INT_ADC3 33 // ADC Sequence 3
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#define INT_PWM3 61 // PWM Generator 3
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#endif
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#endif // __HW_INTS_H__
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