343 lines
17 KiB
C
343 lines
17 KiB
C
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//*****************************************************************************
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//
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// am_hal_pwrctrl.h
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//! @file
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//!
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//! @brief Functions for enabling and disabling power domains.
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//!
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//! @addtogroup pwrctrl2 Power Control
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//! @ingroup apollo2hal
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//! @{
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//*****************************************************************************
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//*****************************************************************************
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//
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// Copyright (c) 2017, Ambiq Micro
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from this
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// software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
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//
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//*****************************************************************************
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#ifndef AM_HAL_PWRCTRL_H
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#define AM_HAL_PWRCTRL_H
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//*****************************************************************************
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//
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// Peripheral enable bits for am_hal_pwrctrl_periph_enable/disable()
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//
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//*****************************************************************************
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#define AM_HAL_PWRCTRL_ADC AM_REG_PWRCTRL_DEVICEEN_ADC_EN
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#define AM_HAL_PWRCTRL_IOM0 AM_REG_PWRCTRL_DEVICEEN_IO_MASTER0_EN
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#define AM_HAL_PWRCTRL_IOM1 AM_REG_PWRCTRL_DEVICEEN_IO_MASTER1_EN
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#define AM_HAL_PWRCTRL_IOM2 AM_REG_PWRCTRL_DEVICEEN_IO_MASTER2_EN
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#define AM_HAL_PWRCTRL_IOM3 AM_REG_PWRCTRL_DEVICEEN_IO_MASTER3_EN
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#define AM_HAL_PWRCTRL_IOM4 AM_REG_PWRCTRL_DEVICEEN_IO_MASTER4_EN
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#define AM_HAL_PWRCTRL_IOM5 AM_REG_PWRCTRL_DEVICEEN_IO_MASTER5_EN
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#define AM_HAL_PWRCTRL_IOS AM_REG_PWRCTRL_DEVICEEN_IO_SLAVE_EN
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#define AM_HAL_PWRCTRL_PDM AM_REG_PWRCTRL_DEVICEEN_PDM_EN
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#define AM_HAL_PWRCTRL_UART0 AM_REG_PWRCTRL_DEVICEEN_UART0_EN
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#define AM_HAL_PWRCTRL_UART1 AM_REG_PWRCTRL_DEVICEEN_UART1_EN
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//*****************************************************************************
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//
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// Macro to set the appropriate IOM peripheral when using
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// am_hal_pwrctrl_periph_enable()/disable().
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// For Apollo2, the module argument must resolve to be a value from 0-5.
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//
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//*****************************************************************************
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#define AM_HAL_PWRCTRL_IOM(module) \
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(AM_REG_PWRCTRL_DEVICEEN_IO_MASTER0_EN << module)
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//*****************************************************************************
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//
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// Macro to set the appropriate UART peripheral when using
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// am_hal_pwrctrl_periph_enable()/disable().
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// For Apollo2, the module argument must resolve to be a value from 0-1.
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//
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//*****************************************************************************
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#define AM_HAL_PWRCTRL_UART(module) \
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(AM_REG_PWRCTRL_DEVICEEN_UART0_EN << module)
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//*****************************************************************************
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//
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// Memory enable values for am_hal_pwrctrl_memory_enable()
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//
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//*****************************************************************************
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#define AM_HAL_PWRCTRL_MEMEN_SRAM8K AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM8K
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#define AM_HAL_PWRCTRL_MEMEN_SRAM16K AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM16K
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#define AM_HAL_PWRCTRL_MEMEN_SRAM24K (AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM16K | \
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AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM2)
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#define AM_HAL_PWRCTRL_MEMEN_SRAM32K AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM32K
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#define AM_HAL_PWRCTRL_MEMEN_SRAM64K AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM64K
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#define AM_HAL_PWRCTRL_MEMEN_SRAM96K \
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(AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM64K | \
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AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP2)
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#define AM_HAL_PWRCTRL_MEMEN_SRAM128K AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM128K
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#define AM_HAL_PWRCTRL_MEMEN_SRAM160K \
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(AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM128K | \
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AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP4)
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#define AM_HAL_PWRCTRL_MEMEN_SRAM192K \
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(AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM128K | \
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AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP4 | \
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AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP5)
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#define AM_HAL_PWRCTRL_MEMEN_SRAM224K \
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(AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM128K | \
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AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP4 | \
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AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP5 | \
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AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP6)
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#define AM_HAL_PWRCTRL_MEMEN_SRAM256K AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM256K
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#define AM_HAL_PWRCTRL_MEMEN_FLASH512K AM_REG_PWRCTRL_MEMEN_FLASH0_EN
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#define AM_HAL_PWRCTRL_MEMEN_FLASH1M \
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(AM_REG_PWRCTRL_MEMEN_FLASH0_EN | \
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AM_REG_PWRCTRL_MEMEN_FLASH1_EN)
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#define AM_HAL_PWRCTRL_MEMEN_CACHE \
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(AM_REG_PWRCTRL_MEMEN_CACHEB0_EN | \
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AM_REG_PWRCTRL_MEMEN_CACHEB2_EN)
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#define AM_HAL_PWRCTRL_MEMEN_CACHE_DIS \
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~(AM_REG_PWRCTRL_MEMEN_CACHEB0_EN | \
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AM_REG_PWRCTRL_MEMEN_CACHEB2_EN)
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//
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// Power up all available memory devices (this is the default power up state)
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//
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#define AM_HAL_PWRCTRL_MEMEN_ALL \
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(AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL | \
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AM_REG_PWRCTRL_MEMEN_FLASH0_EN | \
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AM_REG_PWRCTRL_MEMEN_FLASH1_EN | \
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AM_REG_PWRCTRL_MEMEN_CACHEB0_EN | \
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AM_REG_PWRCTRL_MEMEN_CACHEB2_EN)
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//*****************************************************************************
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//
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// Peripheral power enable and disable delays
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// The delay counts are based on an internal clock that runs at half of
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// HFRC. Therefore, we need to double the delay cycles.
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//
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//*****************************************************************************
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#define AM_HAL_PWRCTRL_DEVICEEN_DELAYCYCLES (22 * 2)
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#define AM_HAL_PWRCTRL_DEVICEDIS_DELAYCYCLES (22 * 2)
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//
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// Use the following only when enabling after sleep (not during initialization).
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//
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#define AM_HAL_PWRCTRL_BUCKEN_DELAYCYCLES (0 * 2)
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#define AM_HAL_PWRCTRL_BUCKDIS_DELAYCYCLES (15 * 2)
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//*****************************************************************************
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//
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// Peripheral PWRONSTATUS groupings.
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//
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//*****************************************************************************
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//
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// Group DEVICEEN bits (per PWRONSTATUS groupings).
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//
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#define AM_HAL_PWRCTRL_DEVICEEN_IOM_0_2 \
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(AM_REG_PWRCTRL_DEVICEEN_IO_MASTER0_EN | \
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AM_REG_PWRCTRL_DEVICEEN_IO_MASTER1_EN | \
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AM_REG_PWRCTRL_DEVICEEN_IO_MASTER2_EN )
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#define AM_HAL_PWRCTRL_DEVICEEN_IOM_3_5 \
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(AM_REG_PWRCTRL_DEVICEEN_IO_MASTER3_EN | \
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AM_REG_PWRCTRL_DEVICEEN_IO_MASTER4_EN | \
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AM_REG_PWRCTRL_DEVICEEN_IO_MASTER5_EN )
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#define AM_HAL_PWRCTRL_DEVICEEN_IOS_UARTS \
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(AM_REG_PWRCTRL_DEVICEEN_UART0_EN | \
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AM_REG_PWRCTRL_DEVICEEN_UART1_EN | \
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AM_REG_PWRCTRL_DEVICEEN_IO_SLAVE_EN )
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#define AM_HAL_PWRCTRL_DEVICEEN_ADC AM_REG_PWRCTRL_DEVICEEN_ADC_EN
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#define AM_HAL_PWRCTRL_DEVICEEN_PDM AM_REG_PWRCTRL_DEVICEEN_PDM_EN
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//
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// Map PWRONSTATUS bits to peripheral groupings.
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//
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#define AM_HAL_PWRCTRL_PWRONSTATUS_IOS_UARTS AM_REG_PWRCTRL_PWRONSTATUS_PDA_M
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#define AM_HAL_PWRCTRL_PWRONSTATUS_IOM_3_5 AM_REG_PWRCTRL_PWRONSTATUS_PDC_M
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#define AM_HAL_PWRCTRL_PWRONSTATUS_IOM_0_2 AM_REG_PWRCTRL_PWRONSTATUS_PDB_M
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#define AM_HAL_PWRCTRL_PWRONSTATUS_ADC AM_REG_PWRCTRL_PWRONSTATUS_PDADC_M
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#define AM_HAL_PWRCTRL_PWRONSTATUS_PDM AM_REG_PWRCTRL_PWRONSTATUS_PD_PDM_M
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#define POLL_PWRSTATUS(ui32Peripheral) \
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if ( 1 ) \
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{ \
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uint32_t ui32PwrOnStat; \
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if ( ui32Peripheral & AM_HAL_PWRCTRL_DEVICEEN_IOM_0_2 ) \
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{ \
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ui32PwrOnStat = AM_HAL_PWRCTRL_PWRONSTATUS_IOM_0_2; \
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} \
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else if ( ui32Peripheral & AM_HAL_PWRCTRL_DEVICEEN_IOM_3_5 ) \
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{ \
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ui32PwrOnStat = AM_HAL_PWRCTRL_PWRONSTATUS_IOM_3_5; \
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} \
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else if ( ui32Peripheral & AM_HAL_PWRCTRL_DEVICEEN_IOS_UARTS ) \
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{ \
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ui32PwrOnStat = AM_HAL_PWRCTRL_PWRONSTATUS_IOS_UARTS; \
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} \
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else if ( ui32Peripheral & AM_HAL_PWRCTRL_DEVICEEN_ADC ) \
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{ \
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ui32PwrOnStat = AM_HAL_PWRCTRL_PWRONSTATUS_ADC; \
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} \
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else if ( ui32Peripheral & AM_HAL_PWRCTRL_DEVICEEN_PDM ) \
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{ \
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ui32PwrOnStat = AM_HAL_PWRCTRL_PWRONSTATUS_PDM; \
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} \
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else \
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{ \
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ui32PwrOnStat = 0xFFFFFFFF; \
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} \
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\
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/* */ \
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/* Wait for the power control setting to take effect. */ \
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/* */ \
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while ( !(AM_REG(PWRCTRL, PWRONSTATUS) & ui32PwrOnStat) ); \
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}
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//*****************************************************************************
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//
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// Memory PWRONSTATUS enable values for am_hal_pwrctrl_memory_enable()
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//
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//*****************************************************************************
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#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_8K \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M
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#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_16K \
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(AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M)
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#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_24K \
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(AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M)
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#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_32K \
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(AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M)
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#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_64K \
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(AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M)
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#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_96K \
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(AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M)
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#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_128K \
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(AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP3_SRAM_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M)
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#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_160K \
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(AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP4_SRAM_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP3_SRAM_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M)
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#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_192K \
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(AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP5_SRAM_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP4_SRAM_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP3_SRAM_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M)
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#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_224K \
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(AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP6_SRAM_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP5_SRAM_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP4_SRAM_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP3_SRAM_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M)
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#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_256K \
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(AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP7_SRAM_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP6_SRAM_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP5_SRAM_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP4_SRAM_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP3_SRAM_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M | \
|
||
|
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M | \
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AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M)
|
||
|
|
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||
|
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#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL \
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AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_256K
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||
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//*****************************************************************************
|
||
|
|
//
|
||
|
|
// Function prototypes
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
extern void am_hal_pwrctrl_periph_enable(uint32_t ui32Peripheral);
|
||
|
|
extern void am_hal_pwrctrl_periph_disable(uint32_t ui32Peripheral);
|
||
|
|
extern bool am_hal_pwrctrl_memory_enable(uint32_t ui32MemEn);
|
||
|
|
extern void am_hal_pwrctrl_bucks_init(void);
|
||
|
|
extern void am_hal_pwrctrl_bucks_enable(void);
|
||
|
|
extern void am_hal_pwrctrl_bucks_disable(void);
|
||
|
|
extern void am_hal_pwrctrl_low_power_init(void);
|
||
|
|
|
||
|
|
#endif // AM_HAL_PWRCTRL_H
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// End Doxygen group.
|
||
|
|
//! @}
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|