2013-05-24 10:04:51 +08:00
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/** @file reg_rti.h
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* @brief RTI Register Layer Header File
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2013-05-29 16:42:26 +08:00
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* @date 29.May.2013
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* @version 03.05.02
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2013-05-24 10:04:51 +08:00
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*
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* This file contains:
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* - Definitions
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* - Types
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* - Interface Prototypes
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* .
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* which are relevant for the RTI driver.
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*/
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/* (c) Texas Instruments 2009-2013, All rights reserved. */
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#ifndef __REG_RTI_H__
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#define __REG_RTI_H__
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#include "sys_common.h"
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/* USER CODE BEGIN (0) */
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/* USER CODE END */
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/* Rti Register Frame Definition */
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/** @struct rtiBase
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* @brief RTI Register Frame Definition
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*
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* This type is used to access the RTI Registers.
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*/
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/** @typedef rtiBASE_t
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* @brief RTI Register Frame Type Definition
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*
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* This type is used to access the RTI Registers.
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*/
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typedef volatile struct rtiBase
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{
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uint32 GCTRL; /**< 0x0000: Global Control Register */
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uint32 TBCTRL; /**< 0x0004: Timebase Control Register */
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uint32 CAPCTRL; /**< 0x0008: Capture Control Register */
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uint32 COMPCTRL; /**< 0x000C: Compare Control Register */
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struct
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{
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uint32 FRCx; /**< 0x0010,0x0030: Free Running Counter x Register */
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uint32 UCx; /**< 0x0014,0x0034: Up Counter x Register */
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uint32 CPUCx; /**< 0x0018,0x0038: Compare Up Counter x Register */
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uint32 rsvd1; /**< 0x001C,0x003C: Reserved */
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uint32 CAFRCx; /**< 0x0020,0x0040: Capture Free Running Counter x Register */
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uint32 CAUCx; /**< 0x0024,0x0044: Capture Up Counter x Register */
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uint32 rsvd2[2U]; /**< 0x0028,0x0048: Reserved */
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} CNT[2U]; /**< Counter x selection:
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- 0: Counter 0
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- 1: Counter 1 */
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struct
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{
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uint32 COMPx; /**< 0x0050,0x0058,0x0060,0x0068: Compare x Register */
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uint32 UDCPx; /**< 0x0054,0x005C,0x0064,0x006C: Update Compare x Register */
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} CMP[4U]; /**< Compare x selection:
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- 0: Compare 0
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- 1: Compare 1
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- 2: Compare 2
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- 3: Compare 3 */
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uint32 TBLCOMP; /**< 0x0070: External Clock Timebase Low Compare Register */
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uint32 TBHCOMP; /**< 0x0074: External Clock Timebase High Compare Register */
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uint32 rsvd3[2U]; /**< 0x0078: Reserved */
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uint32 SETINT; /**< 0x0080: Set/Status Interrupt Register */
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uint32 CLEARINT; /**< 0x0084: Clear/Status Interrupt Register */
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uint32 INTFLAG; /**< 0x0088: Interrupt Flag Register */
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uint32 rsvd4; /**< 0x008C: Reserved */
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uint32 DWDCTRL; /**< 0x0090: Digital Watchdog Control Register */
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uint32 DWDPRLD; /**< 0x0094: Digital Watchdog Preload Register */
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uint32 WDSTATUS; /**< 0x0098: Watchdog Status Register */
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uint32 WDKEY; /**< 0x009C: Watchdog Key Register */
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uint32 DWDCNTR; /**< 0x00A0: Digital Watchdog Down Counter */
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uint32 WWDRXNCTRL; /**< 0x00A4: Digital Windowed Watchdog Reaction Control */
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uint32 WWDSIZECTRL; /**< 0x00A8: Digital Windowed Watchdog Window Size Control */
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uint32 INTCLRENABLE; /**< 0x00AC: RTI Compare Interrupt Clear Enable Register */
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uint32 COMP0CLR; /**< 0x00B0: RTI Compare 0 Clear Register */
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uint32 COMP1CLR; /**< 0x00B4: RTI Compare 1 Clear Register */
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uint32 COMP2CLR; /**< 0x00B8: RTI Compare 2 Clear Register */
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uint32 COMP3CLR; /**< 0x00BC: RTI Compare 3 Clear Register */
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} rtiBASE_t;
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/** @def rtiREG1
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* @brief RTI1 Register Frame Pointer
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*
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* This pointer is used by the RTI driver to access the RTI1 registers.
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*/
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#define rtiREG1 ((rtiBASE_t *)0xFFFFFC00U)
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/* USER CODE BEGIN (1) */
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/* USER CODE END */
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#endif
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