336 lines
18 KiB
C
336 lines
18 KiB
C
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/**************************************************************************//**
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* @file adc.h
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* @version V3.0
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* $Revision: 10 $
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* $Date: 14/02/10 2:27p $
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* @brief M051 series ADC driver header file
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*
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* @note
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* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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#ifndef __ADC_H__
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#define __ADC_H__
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/** @addtogroup M051_Device_Driver M051 Device Driver
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@{
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*/
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/** @addtogroup M051_ADC_Driver ADC Driver
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@{
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*/
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/** @addtogroup M051_ADC_EXPORTED_CONSTANTS ADC Exported Constants
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@{
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*/
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/*---------------------------------------------------------------------------------------------------------*/
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/* ADCR Constant Definitions */
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/*---------------------------------------------------------------------------------------------------------*/
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#define ADC_ADCR_ADEN_CONVERTER_DISABLE (0UL<<ADC_ADCR_ADEN_Pos) /*!< ADC converter disable */
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#define ADC_ADCR_ADEN_CONVERTER_ENABLE (1UL<<ADC_ADCR_ADEN_Pos) /*!< ADC converter enable */
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#define ADC_ADCR_ADMD_SINGLE (0UL<<ADC_ADCR_ADMD_Pos) /*!< Single mode */
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#define ADC_ADCR_ADMD_BURST (1UL<<ADC_ADCR_ADMD_Pos) /*!< Burst mode */
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#define ADC_ADCR_ADMD_SINGLE_CYCLE (2UL<<ADC_ADCR_ADMD_Pos) /*!< Single cycle scan mode */
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#define ADC_ADCR_ADMD_CONTINUOUS (3UL<<ADC_ADCR_ADMD_Pos) /*!< Continuous scan mode */
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#define ADC_ADCR_DIFFEN_SINGLE_END (0UL<<ADC_ADCR_DIFFEN_Pos) /*!< Single end input mode */
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#define ADC_ADCR_DIFFEN_DIFFERENTIAL (1UL<<ADC_ADCR_DIFFEN_Pos) /*!< Differential input type */
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#define ADC_ADCR_DMOF_UNSIGNED_OUTPUT (0UL<<ADC_ADCR_DMOF_Pos) /*!< Select the straight binary format as the output format of the conversion result */
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#define ADC_ADCR_DMOF_TWOS_COMPLEMENT (1UL<<ADC_ADCR_DMOF_Pos) /*!< Select the 2's complement format as the output format of the conversion result */
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#define ADC_ADCR_TRGEN_DISABLE (0UL<<ADC_ADCR_TRGEN_Pos) /*!< Disable triggering of A/D conversion by external STADC pin or PWM */
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#define ADC_ADCR_TRGEN_ENABLE (1UL<<ADC_ADCR_TRGEN_Pos) /*!< Enable triggering of A/D conversion by external STADC pin or PWM */
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#define ADC_ADCR_TRGS_STADC (0UL<<ADC_ADCR_TRGS_Pos) /*!< A/D conversion is started by external STADC pin */
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#define ADC_ADCR_TRGS_PWM (3UL<<ADC_ADCR_TRGS_Pos) /*!< A/D conversion is started by PWM */
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#define ADC_ADCR_TRGCOND_LOW_LEVEL (0UL<<ADC_ADCR_TRGCOND_Pos) /*!< STADC Low level active */
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#define ADC_ADCR_TRGCOND_HIGH_LEVEL (1UL<<ADC_ADCR_TRGCOND_Pos) /*!< STADC High level active */
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#define ADC_ADCR_TRGCOND_FALLING_EDGE (2UL<<ADC_ADCR_TRGCOND_Pos) /*!< STADC Falling edge active */
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#define ADC_ADCR_TRGCOND_RISING_EDGE (3UL<<ADC_ADCR_TRGCOND_Pos) /*!< STADC Rising edge active */
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/*---------------------------------------------------------------------------------------------------------*/
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/* ADCHER Constant Definitions */
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/*---------------------------------------------------------------------------------------------------------*/
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#define ADC_ADCHER_PRESEL_EXT_INPUT_SIGNAL (0UL<<ADC_ADCHER_PRESEL_Pos) /*!< The input source of channel 7 is the external analog input */
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#define ADC_ADCHER_PRESEL_INT_BANDGAP (1UL<<ADC_ADCHER_PRESEL_Pos) /*!< The input source of channel 7 is the internal bandgap voltage */
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#define ADC_ADCHER_PRESEL_INT_TEMPERATURE_SENSOR (2UL<<ADC_ADCHER_PRESEL_Pos) /*!< The input source of channel 7 is the output of internal temperature sensor */
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/*---------------------------------------------------------------------------------------------------------*/
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/* ADCMPR Constant Definitions */
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/*---------------------------------------------------------------------------------------------------------*/
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#define ADC_ADCMPR_CMPD(x) ((x) << ADC_ADCMPR_CMPD_Pos) /*!< Compare value for compare function */
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#define ADC_ADCMPR_CMPMATCNT(x) (((x)-1) << ADC_ADCMPR_CMPMATCNT_Pos) /*!< Match count for compare function */
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#define ADC_ADCMPR_CMPCH(x) ((x) << ADC_ADCMPR_CMPCH_Pos) /*!< Compare channel for compare function */
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#define ADC_ADCMPR_CMPCOND_LESS_THAN (0<<ADC_ADCMPR_CMPCOND_Pos) /*!< The compare condition is "less than" */
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#define ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL (1<<ADC_ADCMPR_CMPCOND_Pos) /*!< The compare condition is "greater than or equal to" */
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#define ADC_ADCMPR_CMPIE_INTERRUPT_ENABLE (ADC_ADCMPR_CMPIE_Msk) /*!< The compare function interrupt enable */
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/*---------------------------------------------------------------------------------------------------------*/
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/* ADC Interrupt Constant Definitions */
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/*---------------------------------------------------------------------------------------------------------*/
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#define ADC_ADF_INT (ADC_ADSR_ADF_Msk) /*!< ADC convert complete interrupt */
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#define ADC_CMP0_INT (ADC_ADSR_CMPF0_Msk) /*!< ADC comparator 0 interrupt */
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#define ADC_CMP1_INT (ADC_ADSR_CMPF1_Msk) /*!< ADC comparator 1 interrupt */
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/*---------------------------------------------------------------------------------------------------------*/
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/* ADC Operation Mode Constant Definitions */
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/*---------------------------------------------------------------------------------------------------------*/
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#define ADC_SINGLE_MODE 0 /*!< ADC single mode */
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#define ADC_BURST_MODE 1 /*!< ADC burst mode */
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#define ADC_SINGLE_CYCLE_MODE 2 /*!< ADC single-cycle scan mode */
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#define ADC_CONTINUOUS_MODE 3 /*!< ADC continuous scan mode */
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/*---------------------------------------------------------------------------------------------------------*/
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/* ADC Trigger Condition Constant Definitions */
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/*---------------------------------------------------------------------------------------------------------*/
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#define ADC_LOW_LEVEL 0 /*!< ADC external trigger condition is low level trigger */
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#define ADC_HIGH_LEVEL 1 /*!< ADC external trigger condition is high level trigger */
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#define ADC_FALLING_EDGE 2 /*!< ADC external trigger condition is falling edge trigger */
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#define ADC_RISING_EDGE 3 /*!< ADC external trigger condition is rising edge trigger */
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/*---------------------------------------------------------------------------------------------------------*/
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/* ADC Compare Condition Constant Definitions */
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/*---------------------------------------------------------------------------------------------------------*/
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#define ADC_LESS_THAN 0 /*!< ADC compare condition is "less than the compare value" */
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#define ADC_GREATER_OR_EQUAL 1 /*!< ADC compare condition is "greater than or equal to the compare value" */
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/*---------------------------------------------------------------------------------------------------------*/
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/* Constant Definitions of ADC Channel 7 Input Source */
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/*---------------------------------------------------------------------------------------------------------*/
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#define ADC_CH7_EXT_INPUT_SIGNAL 0 /*!< External input signal */
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#define ADC_CH7_INT_BANDGAP 1 /*!< Internal band-gap voltage */
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#define ADC_CH7_INT_TEMPERATURE_SENSOR 2 /*!< Internal temperature sensor */
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/*@}*/ /* end of group M051_ADC_EXPORTED_CONSTANTS */
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/** @addtogroup M051_ADC_EXPORTED_FUNCTIONS ADC Exported Functions
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@{
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*/
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/**
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* @brief Configure the analog input source of channel 7.
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* @param[in] adc Base address of ADC module.
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* @param[in] u32Source Decides the analog input source of channel 7. Valid values are:
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* - \ref ADC_ADCHER_PRESEL_EXT_INPUT_SIGNAL : External analog input.
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* - \ref ADC_ADCHER_PRESEL_INT_BANDGAP : Internal bandgap voltage.
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* - \ref ADC_ADCHER_PRESEL_INT_TEMPERATURE_SENSOR : Output of internal temperature sensor.
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* @return None
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* @note While using VBG as channel 7 source, ADC module clock must /b not exceed 300kHz.
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*/
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#define ADC_CONFIG_CH7(adc, u32Source) (ADC->ADCHER = (ADC->ADCHER & ~ADC_ADCHER_PRESEL_Msk) | (u32Source))
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/**
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* @brief Get conversion data of specified channel.
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* @param[in] adc Base address of ADC module.
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* @param[in] u32ChNum ADC Channel, valid value are from 0 to 7.
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* @return Read RSLT bit field to get conversion data.
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*/
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#define ADC_GET_CONVERSION_DATA(adc, u32ChNum) ((ADC->ADDR[(u32ChNum)] & ADC_ADDR_RSLT_Msk)>>ADC_ADDR_RSLT_Pos)
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/**
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* @brief Return the user-specified interrupt flags.
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* @param[in] adc Base address of ADC module.
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* @param[in] u32Mask The combination of following interrupt status bits. Each bit corresponds to a interrupt status.
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* Valid values are:
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* - \ref ADC_ADF_INT :Convert complete interrupt flag.
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* - \ref ADC_CMP0_INT :Comparator 0 interrupt flag.
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* - \ref ADC_CMP1_INT :Comparator 1 interrupt flag.
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* @return User specified interrupt flags.
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*/
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#define ADC_GET_INT_FLAG(adc, u32Mask) (ADC->ADSR & (u32Mask))
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/**
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* @brief This macro clear the selected interrupt status bits.
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* @param[in] adc Base address of ADC module.
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* @param[in] u32Mask The combination of following interrupt status bits. Each bit corresponds to a interrupt status.
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* Valid values are:
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* - \ref ADC_ADF_INT :Convert complete interrupt flag
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* - \ref ADC_CMP0_INT :Comparator 0 interrupt flag
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* - \ref ADC_CMP1_INT :Comparator 1 interrupt flag
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* @return None
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*/
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#define ADC_CLR_INT_FLAG(adc, u32Mask) (ADC->ADSR = u32Mask)
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/**
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* @brief Get the busy state of ADC.
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* @param[in] adc Base address of ADC module.
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* @return busy state of ADC.
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* @retval 0 ADC is not busy.
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* @retval 1 ADC is busy.
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*/
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#define ADC_IS_BUSY(adc) (ADC->ADSR & ADC_ADSR_BUSY_Msk ? 1 : 0)
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/**
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* @brief Check if the ADC conversion data is over written or not.
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* @param[in] adc Base address of ADC module.
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* @param[in] u32ChNum ADC Channel, valid value are from 0 to 7.
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* @return Over run state of ADC data.
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* @retval 0 ADC data is not overrun.
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* @retval 1 ADC data us overrun.
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*/
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#define ADC_IS_DATA_OVERRUN(adc, u32ChNum) (ADC->ADSR & (u32ChNum<<ADC_ADSR_OVERRUN_Pos) ? 1 : 0)
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/**
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* @brief Check if the ADC conversion data is valid or not.
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* @param[in] adc Base address of ADC module.
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* @param[in] u32ChNum ADC Channel, valid value are from 0 to 7.
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* @return Valid state of ADC data.
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* @retval 0 ADC data is not valid.
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* @retval 1 ADC data us valid.
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*/
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#define ADC_IS_DATA_VALID(adc, u32ChNum) (ADC->ADSR & (0x1<<(ADC_ADSR_VALID_Pos+u32ChNum)) ? 1 : 0)
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/**
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* @brief Power down ADC module.
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* @param[in] adc Base address of ADC module.
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* @return None
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*/
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#define ADC_POWER_DOWN(adc) (ADC->ADCR &= ~ADC_ADCR_ADEN_Msk)
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/**
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* @brief Power on ADC module.
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* @param[in] adc Base address of ADC module.
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* @return None
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*/
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#define ADC_POWER_ON(adc) (ADC->ADCR |= ADC_ADCR_ADEN_Msk)
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/**
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* @brief Configure the comparator 0 and enable it.
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* @param[in] adc Base address of ADC module.
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* @param[in] u32ChNum Specifies the source channel, valid value are from 0 to 7.
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* @param[in] u32Condition Specifies the compare condition. Valid values are:
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* - \ref ADC_ADCMPR_CMPCOND_LESS_THAN :The compare condition is "less than the compare value"
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* - \ref ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value
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* @param[in] u32Data Specifies the compare value, valid value are between 0 ~ 0xFFF.
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* @param[in] u32MatchCount Specifies the match count setting, valid values are between 1~16.
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* @return None
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* @details For example, ADC_ENABLE_CMP0(ADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10);
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* Means ADC will assert comparator 0 flag if channel 5 conversion result is greater or
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* equal to 0x800 for 10 times continuously.
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* @note When DIFFEN bit is set to 1, ADC comparator compares CMPD with conversion result with unsigned
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* format (M05xxBN only). u32Data should be filled in unsigned format (straight binary format).
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*/
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#define ADC_ENABLE_CMP0(adc, \
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u32ChNum, \
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u32Condition, \
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u32Data, \
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u32MatchCount) (ADC->ADCMPR[0] = ((u32ChNum) << ADC_ADCMPR_CMPCH_Pos) | \
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u32Condition | \
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((u32Data) << ADC_ADCMPR_CMPD_Pos) | \
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(((u32MatchCount) - 1) << ADC_ADCMPR_CMPMATCNT_Pos) |\
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ADC_ADCMPR_CMPEN_Msk)
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/**
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* @brief Disable comparator 0
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* @param[in] adc Base address of ADC module
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*/
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#define ADC_DISABLE_CMP0(adc) (ADC->ADCMPR[0] = 0)
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/**
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* @brief Configure the comparator 1 and enable it.
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* @param[in] adc Base address of ADC module.
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* @param[in] u32ChNum Specifies the source channel, valid value are from 0 to 7.
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* @param[in] u32Condition Specifies the compare condition. Valid values are:
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* - \ref ADC_ADCMPR_CMPCOND_LESS_THAN :The compare condition is "less than the compare value"
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* - \ref ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value
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* @param[in] u32Data Specifies the compare value, valid value are between 0 ~ 0xFFF.
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* @param[in] u32MatchCount Specifies the match count setting, valid values are between 1~16.
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* @return None
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* @details For example, ADC_ENABLE_CMP1(ADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10);
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* Means ADC will assert comparator 1 flag if channel 5 conversion result is greater or
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* equal to 0x800 for 10 times continuously.
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*/
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#define ADC_ENABLE_CMP1(adc, \
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u32ChNum, \
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u32Condition, \
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u32Data, \
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u32MatchCount) (ADC->ADCMPR[1] = ((u32ChNum) << ADC_ADCMPR_CMPCH_Pos) | \
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u32Condition | \
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((u32Data) << ADC_ADCMPR_CMPD_Pos) | \
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(((u32MatchCount) - 1) << ADC_ADCMPR_CMPMATCNT_Pos) |\
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ADC_ADCMPR_CMPEN_Msk)
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/**
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* @brief Disable comparator 1.
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* @param[in] adc Base address of ADC module.
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*/
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#define ADC_DISABLE_CMP1(adc) (ADC->ADCMPR[1] = 0)
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/**
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* @brief Set ADC input channel. Enabled channel will be converted while ADC starts.
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* @param[in] adc Base address of ADC module.
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* @param[in] u32Mask Channel enable bit. Each bit corresponds to a input channel. Bit 0 is channel 0, bit 1 is channel 1..., bit 7 is channel 7.
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* @return None
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* @note M051 series MCU ADC can only convert 1 channel at a time. If more than 1 channels are enabled, only channel
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* with smallest number will be convert.
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*/
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#define ADC_SET_INPUT_CHANNEL(adc, u32Mask) (ADC->ADCHER = (ADC->ADCHER & ~ADC_ADCHER_CHEN_Msk) | (u32Mask))
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/**
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* @brief Set the output format mode.
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* @param[in] adc Base address of ADC module.
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* @param[in] u32Format Decides the output format. Valid values are:
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* - \ref ADC_ADCR_DMOF_UNSIGNED_OUTPUT :Select the straight binary format as the output format of the conversion result.
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* - \ref ADC_ADCR_DMOF_TWOS_COMPLEMENT :Select the 2's complement format as the output format of the conversion result.
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* @return None
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* @note Burst mode and ADC compare function can not support 2's complement output format,
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* this u32Format must be 0 (M05xxBN only).
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*/
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#define ADC_SET_DMOF(adc, u32Format) (ADC->ADCR = (ADC->ADCR & ~ADC_ADCR_DMOF_Msk) | (u32Format))
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/**
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* @brief Start the A/D conversion.
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* @param[in] adc Base address of ADC module.
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* @return None
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*/
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#define ADC_START_CONV(adc) (ADC->ADCR |= ADC_ADCR_ADST_Msk)
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/**
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* @brief Stop the A/D conversion.
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* @param[in] adc Base address of ADC module.
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* @return None
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* @note When hardware clears the ADST bit, the ADST bit must be kept at 0 at least one ADC peripheral clock
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* period before setting it to 1 again, otherwise the A/D converter may not work (M05xxBN only). If ADST
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* bit is cleared to 0 when ADC is in converting, the BUSY bit will be cleared to 0 immediately, ADC will
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* finish the current conversion and save the result to the ADDRx register of the enabled channel (M05xxBN only).
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* But, ADC can not finish the current conversion and A/D converter enters idle state directly (M05xxDN only).
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*/
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#define ADC_STOP_CONV(adc) (ADC->ADCR &= ~ADC_ADCR_ADST_Msk)
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void ADC_Open(ADC_T *adc,
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uint32_t u32InputMode,
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uint32_t u32OpMode,
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uint32_t u32ChMask);
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void ADC_Close(ADC_T *adc);
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void ADC_EnableHWTrigger(ADC_T *adc,
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uint32_t u32Source,
|
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|
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uint32_t u32Param);
|
||
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void ADC_DisableHWTrigger(ADC_T *adc);
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void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask);
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void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask);
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/*@}*/ /* end of group M051_ADC_EXPORTED_FUNCTIONS */
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/*@}*/ /* end of group M051_ADC_Driver */
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/*@}*/ /* end of group M051_Device_Driver */
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||
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#ifdef __cplusplus
|
||
|
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}
|
||
|
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#endif
|
||
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|
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#endif //__ADC_H__
|
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/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
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