281 lines
10 KiB
C
281 lines
10 KiB
C
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/*
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* File : drv_sdram.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2016, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2016-08-20 xuzhuoyi The first version for STM32F42x
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* 2017-04-07 lizhen9880 Use SDRAM BANK1
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "drv_sdram.h"
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#include "stm32f4xx_ll_fmc.h"
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#include <rtdevice.h>
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#include "board.h"
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#include "drv_mpu.h"
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SDRAM_HandleTypeDef hsdram1;
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FMC_SDRAM_CommandTypeDef command;
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/**
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* @brief SDRAM MSP Initialization
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* This function configures the hardware resources used in this example:
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* - Peripheral's clock enable
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* - Peripheral's GPIO Configuration
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* @param hsdram: SDRAM handle pointer
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* @retval None
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*/
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void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
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{
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GPIO_InitTypeDef GPIO_Init_Structure;
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/*##-1- Enable peripherals and GPIO Clocks #################################*/
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/* Enable GPIO clocks */
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__HAL_RCC_GPIOB_CLK_ENABLE();
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__HAL_RCC_GPIOC_CLK_ENABLE();
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__HAL_RCC_GPIOD_CLK_ENABLE();
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__HAL_RCC_GPIOE_CLK_ENABLE();
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__HAL_RCC_GPIOF_CLK_ENABLE();
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__HAL_RCC_GPIOG_CLK_ENABLE();
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/* Enable FMC clock */
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__HAL_RCC_FMC_CLK_ENABLE();
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/*##-2- Configure peripheral GPIO ##########################################*/
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/*-- GPIOs Configuration -----------------------------------------------------*/
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/*
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+-------------------+--------------------+--------------------+--------------------+
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+ SDRAM pins assignment +
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+-------------------+--------------------+--------------------+--------------------+
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| PD0 <-> FMC_D2 | PE0 <-> FMC_NBL0 | PF0 <-> FMC_A0 | PG0 <-> FMC_A10 |
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| PD1 <-> FMC_D3 | PE1 <-> FMC_NBL1 | PF1 <-> FMC_A1 | PG1 <-> FMC_A11 |
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| PD8 <-> FMC_D13 | PE7 <-> FMC_D4 | PF2 <-> FMC_A2 | PG2 <-> FMC_A12 |
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| PD9 <-> FMC_D14 | PE8 <-> FMC_D5 | PF3 <-> FMC_A3 | PG4 <-> FMC_BA0 |
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| PD10 <-> FMC_D15 | PE9 <-> FMC_D6 | PF4 <-> FMC_A4 | PG5 <-> FMC_BA1 |
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| PD14 <-> FMC_D0 | PE10 <-> FMC_D7 | PF5 <-> FMC_A5 | PG8 <-> FMC_SDCLK |
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| PD15 <-> FMC_D1 | PE11 <-> FMC_D8 | PF11 <-> FMC_NRAS | PG15 <-> FMC_NCAS |
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+-------------------| PE12 <-> FMC_D9 | PF12 <-> FMC_A6 |--------------------+
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| PE13 <-> FMC_D10 | PF13 <-> FMC_A7 |
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| PE14 <-> FMC_D11 | PF14 <-> FMC_A8 |
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| PE15 <-> FMC_D12 | PF15 <-> FMC_A9 |
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+-------------------+--------------------+--------------------+
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| PC3 <-> FMC_SDCKE0|
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| PC2 <-> FMC_SDNE0 |
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| PC0 <-> FMC_SDNWE |
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+-------------------+
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*/
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/* Common GPIO configuration */
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GPIO_Init_Structure.Mode = GPIO_MODE_AF_PP;
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GPIO_Init_Structure.Speed = GPIO_SPEED_HIGH;
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GPIO_Init_Structure.Pull = GPIO_PULLUP;
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GPIO_Init_Structure.Alternate = GPIO_AF12_FMC;
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/* GPIOC configuration */
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GPIO_Init_Structure.Pin = GPIO_PIN_0 | GPIO_PIN_2 | GPIO_PIN_3;
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HAL_GPIO_Init(GPIOC, &GPIO_Init_Structure);
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/* GPIOD configuration */
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GPIO_Init_Structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8 |
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GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_14 |
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GPIO_PIN_15;
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HAL_GPIO_Init(GPIOD, &GPIO_Init_Structure);
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/* GPIOE configuration */
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GPIO_Init_Structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7 |
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GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 |
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GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 |
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GPIO_PIN_14 | GPIO_PIN_15;
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HAL_GPIO_Init(GPIOE, &GPIO_Init_Structure);
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/* GPIOF configuration */
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GPIO_Init_Structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 |
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GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 |
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GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 |
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GPIO_PIN_14 | GPIO_PIN_15;
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HAL_GPIO_Init(GPIOF, &GPIO_Init_Structure);
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/* GPIOG configuration */
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GPIO_Init_Structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 |
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GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_15;
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HAL_GPIO_Init(GPIOG, &GPIO_Init_Structure);
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}
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/**
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* @brief SDRAM MSP De-Initialization
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* This function frees the hardware resources used in this example:
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* - Disable the Peripheral's clock
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* - Revert GPIO configuration to their default state
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* @param hsdram: SDRAM handle pointer
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* @retval None
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*/
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void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)
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{
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/*## Disable peripherals and GPIO Clocks ###################################*/
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HAL_GPIO_DeInit(GPIOC, GPIO_PIN_0 | GPIO_PIN_2 | GPIO_PIN_3);
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HAL_GPIO_DeInit(GPIOD, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8 |\
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GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_14 |\
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GPIO_PIN_15);
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HAL_GPIO_DeInit(GPIOE, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7 |\
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GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 |\
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GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 |\
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GPIO_PIN_14 | GPIO_PIN_15);
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HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 |\
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GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 |\
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GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 |\
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GPIO_PIN_14 | GPIO_PIN_15);
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HAL_GPIO_DeInit(GPIOG, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 |\
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GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_15);
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}
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/**
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* @brief Perform the SDRAM exernal memory inialization sequence
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* @param hsdram: SDRAM handle
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* @param Command: Pointer to SDRAM command structure
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* @retval None
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*/
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static void SDRAM_Initialization_Sequence(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command)
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{
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__IO uint32_t tmpmrd =0;
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/* Step 3: Configure a clock configuration enable command */
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Command->CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
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Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
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Command->AutoRefreshNumber = 1;
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Command->ModeRegisterDefinition = 0;
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/* Send the command */
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HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);
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/* Step 4: Insert 100 ms delay */
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/* interrupt is not enable, just to delay some time. */
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for (tmpmrd = 0; tmpmrd < 0xfffff; tmpmrd ++)
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;
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/* Step 5: Configure a PALL (precharge all) command */
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Command->CommandMode = FMC_SDRAM_CMD_PALL;
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Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
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Command->AutoRefreshNumber = 1;
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Command->ModeRegisterDefinition = 0;
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/* Send the command */
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HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);
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/* Step 6 : Configure a Auto-Refresh command */
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Command->CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
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Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
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Command->AutoRefreshNumber = 8;
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Command->ModeRegisterDefinition = 0;
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/* Send the command */
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HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);
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/* Step 7: Program the external memory mode register */
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tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |
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SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |
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SDRAM_MODEREG_CAS_LATENCY_3 |
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SDRAM_MODEREG_OPERATING_MODE_STANDARD |
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SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
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Command->CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
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Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
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Command->AutoRefreshNumber = 1;
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Command->ModeRegisterDefinition = tmpmrd;
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/* Send the command */
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HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);
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/* Step 8: Set the refresh rate counter */
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/* (15.62 us x Freq) - 20 */
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/* Set the device refresh counter */
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HAL_SDRAM_ProgramRefreshRate(hsdram, REFRESH_COUNT);
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}
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/**
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* @brief Configures the FMC and GPIOs to interface with the SDRAM memory.
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* This function must be called before any read/write operation
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* on the SDRAM.
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* @param None
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* @retval None
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*/
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void SDRAM_Init(void)
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{
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FMC_SDRAM_TimingTypeDef SDRAM_Timing;
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/*##-1- Configure the SDRAM device #########################################*/
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/* SDRAM device configuration */
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hsdram1.Instance = FMC_SDRAM_DEVICE;
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/* Timing configuration for 90 MHz of SD clock frequency (180MHz/2) */
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/* TMRD: 2 Clock cycles */
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SDRAM_Timing.LoadToActiveDelay = 2;
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/* TXSR: min=70ns (6x11.90ns) */
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SDRAM_Timing.ExitSelfRefreshDelay = 8;
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/* TRAS: min=42ns (4x11.90ns) max=120k (ns) */
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SDRAM_Timing.SelfRefreshTime = 6;
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/* TRC: min=63 (6x11.90ns) */
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SDRAM_Timing.RowCycleDelay = 6;
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/* TWR: 2 Clock cycles */
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SDRAM_Timing.WriteRecoveryTime = 2;
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/* TRP: 15ns => 2x11.90ns */
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SDRAM_Timing.RPDelay = 2;
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/* TRCD: 15ns => 2x11.90ns */
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SDRAM_Timing.RCDDelay = 2;
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hsdram1.Init.SDBank = FMC_SDRAM_BANK1;
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hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_9;
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hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_13;
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hsdram1.Init.MemoryDataWidth = SDRAM_MEMORY_WIDTH;
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hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
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hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_3;
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hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
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hsdram1.Init.SDClockPeriod = SDCLOCK_PERIOD;
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hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE;
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hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_1;
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/* Initialize the SDRAM controller */
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if(HAL_SDRAM_Init(&hsdram1, &SDRAM_Timing) != HAL_OK)
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{
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/* Initialization Error */
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Error_Handler();
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}
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/* Program the SDRAM external device */
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SDRAM_Initialization_Sequence(&hsdram1, &command);
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}
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rt_err_t sdram_hw_init(void)
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{
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SDRAM_Init();
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return RT_EOK;
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}
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static int rt_sdram_hw_init(void)
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{
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return (int)sdram_hw_init();
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}
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INIT_BOARD_EXPORT(rt_sdram_hw_init);
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