132 lines
3.6 KiB
C
132 lines
3.6 KiB
C
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/*
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* File : cpu.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2016<EFBFBD><EFBFBD>9<EFBFBD><EFBFBD>8<EFBFBD><EFBFBD> Urey the first version
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*/
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#include <rtthread.h>
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#include <board.h>
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#include <rthw.h>
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#include "../common/mips.h"
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mips32_core_cfg_t g_mips_core =
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{
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.icache_line_size = 32,
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.icache_size = 16384,
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.dcache_line_size = 32,
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.dcache_size = 16384,
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.max_tlb_entries = 16, /* max_tlb_entries */
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};
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void rt_hw_tlb_init(void)
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{
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//----------------------------------------------------------------------------------
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//cchappy tlb 0x30000000 to 0xC0000000
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//----------------------------------------------------------------------------------
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unsigned int pagemask = 0x007fe000;//0x01ffe000; /* 4MB */
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/* cached D:allow-W V:valid G */
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unsigned int entrylo0 = (0x30000000 >> 6) | (3 << 3) + (1 << 2) + (1 << 1) + 1;
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unsigned int entrylo1 = (0x30400000 >> 6) | (3 << 3) + (1 << 2) + (1 << 1) + 1;
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unsigned int entryhi = 0xc0000000; /* kseg2 base */
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int i;
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__write_32bit_c0_register($5, 4, 0xa9000000);
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write_c0_pagemask(pagemask);
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write_c0_wired(0);
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/* indexed write 32 tlb entry */
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for(i = 0; i < 32; i++)
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{
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asm (
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".macro _ssnop; sll $0, $0, 1; .endm\n\t"
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".macro _ehb; sll $0, $0, 3; .endm\n\t"
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".macro mtc0_tlbw_hazard; _ssnop; _ssnop; _ehb; .endm\n\t"
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".macro tlbw_use_hazard; _ssnop; _ssnop; _ssnop; _ehb; .endm\n\t"
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"\n\t"
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"mtc0 %0, $0\n\t" /* write Index */
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"tlbw_use_hazard\n\t"
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"mtc0 %1, $5\n\t" /* write PageMask */
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"mtc0 %2, $10\n\t" /* write EntryHi */
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"mtc0 %3, $2\n\t" /* write EntryLo0 */
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"mtc0 %4, $3\n\t" /* write EntryLo1 */
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"mtc0_tlbw_hazard\n\t"
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"tlbwi \n\t" /* TLB indexed write */
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"tlbw_use_hazard\n\t"
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: : "Jr" (i), "r" (pagemask), "r" (entryhi),
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"r" (entrylo0), "r" (entrylo1)
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);
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entryhi += 0x0800000; /* 32MB */
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entrylo0 += (0x0800000 >> 6);
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entrylo1 += (0x0800000 >> 6);
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}
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}
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void rt_hw_cache_init(void)
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{
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r4k_cache_flush_all();
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}
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/**
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* this function will reset CPU
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*
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*/
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RT_WEAK void rt_hw_cpu_reset()
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{
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/* open the watch-dog */
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REG_WDT_TCSR = WDT_TCSR_EXT_EN;
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REG_WDT_TCSR |= WDT_TCSR_PRESCALE_1024;
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REG_WDT_TDR = 0x03;
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REG_WDT_TCNT = 0x00;
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REG_WDT_TCER |= WDT_TCER_TCEN;
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rt_kprintf("reboot system...\n");
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rt_hw_interrupt_disable();
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while (1);
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}
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/**
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* this function will shutdown CPU
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*
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*/
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RT_WEAK void rt_hw_cpu_shutdown()
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{
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rt_kprintf("shutdown...\n");
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rt_hw_interrupt_disable();
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while (1);
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}
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/**
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* This function finds the first bit set (beginning with the least significant bit)
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* in value and return the index of that bit.
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*
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* Bits are numbered starting at 1 (the least significant bit). A return value of
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* zero from any of these functions means that the argument was zero.
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*
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* @return return the index of the first bit set. If value is 0, then this function
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* shall return 0.
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*/
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RT_WEAK int __rt_ffs(int value)
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{
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return __builtin_ffs(value);
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}
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