414 lines
11 KiB
C
414 lines
11 KiB
C
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/*
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* This file is part of FH8620 BSP for RT-Thread distribution.
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*
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* Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
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* All rights reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Visit http://www.fullhan.com to get contact with Fullhan.
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*
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* Change Logs:
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* Date Author Notes
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*/
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#include "inc/fh_driverlib.h"
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// *1: card off
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// *0: card on
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inline rt_uint32_t MMC_GetCardStatus(struct fh_mmc_obj *mmc_obj)
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{
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rt_uint32_t card_status = GET_REG(mmc_obj->base + OFFSET_SDC_CDETECT);
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return card_status & 0x1;
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}
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inline void MMC_StartDma(struct fh_mmc_obj *mmc_obj)
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{
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rt_uint32_t reg;
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SET_REG(mmc_obj->base + OFFSET_SDC_DBADDR, (rt_uint32_t)mmc_obj->descriptors);
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reg = GET_REG(mmc_obj->base + OFFSET_SDC_BMOD);
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reg |= 1 << 7;
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SET_REG(mmc_obj->base + OFFSET_SDC_BMOD, reg);
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}
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inline void MMC_StopDma(struct fh_mmc_obj *mmc_obj)
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{
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rt_uint32_t reg;
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reg = GET_REG(mmc_obj->base + OFFSET_SDC_BMOD);
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reg &= ~(1 << 7);
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SET_REG(mmc_obj->base + OFFSET_SDC_BMOD, reg);
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}
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void MMC_InitDescriptors(struct fh_mmc_obj *mmc_obj, rt_uint32_t *buf, rt_uint32_t size)
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{
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MMC_DMA_Descriptors *desc;
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rt_uint32_t len = 0;
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int i, desc_cnt = 0;
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desc = mmc_obj->descriptors;
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while(size > 0)
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{
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desc[desc_cnt].desc0.bit.own = 1;
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desc[desc_cnt].desc0.bit.sencond_address_chained = 1;
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desc[desc_cnt].desc1.bit.buffer1_size = MIN(MMC_DMA_DESC_BUFF_SIZE, size);
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desc[desc_cnt].desc2.bit.buffer_addr0 = (rt_uint32_t)buf + len;
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desc[desc_cnt].desc3.bit.buffer_addr1 = (rt_uint32_t)mmc_obj->descriptors + (desc_cnt + 1) * sizeof(MMC_DMA_Descriptors);
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size -= desc[desc_cnt].desc1.bit.buffer1_size;
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len += desc[desc_cnt].desc1.bit.buffer1_size;
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desc_cnt++;
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}
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desc[0].desc0.bit.first_descriptor = 1;
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desc[desc_cnt-1].desc0.bit.last_descriptor = 1;
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desc[desc_cnt-1].desc3.bit.buffer_addr1 = 0;
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}
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inline rt_uint32_t MMC_GetWaterlevel(struct fh_mmc_obj *mmc_obj)
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{
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return (GET_REG(mmc_obj->base + OFFSET_SDC_STATUS) >> 17) & 0x1fff;
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}
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inline rt_uint32_t MMC_GetStatus(struct fh_mmc_obj *mmc_obj)
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{
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return GET_REG(mmc_obj->base + OFFSET_SDC_STATUS);
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}
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inline rt_uint32_t MMC_GetRawInterrupt(struct fh_mmc_obj *mmc_obj)
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{
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return GET_REG(mmc_obj->base + OFFSET_SDC_RINTSTS);
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}
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inline rt_uint32_t MMC_GetUnmaskedInterrupt(struct fh_mmc_obj *mmc_obj)
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{
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return GET_REG(mmc_obj->base + OFFSET_SDC_MINTSTS);
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}
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inline rt_uint32_t MMC_ClearRawInterrupt(struct fh_mmc_obj *mmc_obj, rt_uint32_t interrupts)
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{
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return SET_REG(mmc_obj->base + OFFSET_SDC_RINTSTS, interrupts);
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}
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inline rt_uint32_t MMC_GetInterruptMask(struct fh_mmc_obj *mmc_obj)
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{
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return GET_REG(mmc_obj->base + OFFSET_SDC_INTMASK);
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}
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inline rt_uint32_t MMC_SetInterruptMask(struct fh_mmc_obj *mmc_obj, rt_uint32_t mask)
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{
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return SET_REG(mmc_obj->base + OFFSET_SDC_INTMASK, mask);
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}
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inline void MMC_SetByteCount(struct fh_mmc_obj *mmc_obj, rt_uint32_t bytes)
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{
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SET_REG(mmc_obj->base + OFFSET_SDC_BYTCNT, bytes);
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}
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inline void MMC_SetBlockSize(struct fh_mmc_obj *mmc_obj, rt_uint32_t size)
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{
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SET_REG(mmc_obj->base + OFFSET_SDC_BLKSIZ, size);
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}
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inline rt_uint32_t MMC_GetResponse(struct fh_mmc_obj *mmc_obj, int resp_num)
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{
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return GET_REG(mmc_obj->base + OFFSET_SDC_RESP0 + resp_num * 4);
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}
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inline rt_uint32_t MMC_IsFifoEmpty(struct fh_mmc_obj *mmc_obj)
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{
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return (GET_REG(mmc_obj->base + OFFSET_SDC_STATUS) >> 2) & 0x1;
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}
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inline rt_uint32_t MMC_IsDataStateBusy(struct fh_mmc_obj *mmc_obj)
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{
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return (GET_REG(mmc_obj->base + OFFSET_SDC_STATUS) >> 10) & 0x1;
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}
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int MMC_WriteData(struct fh_mmc_obj *mmc_obj, rt_uint32_t *buf, rt_uint32_t size)
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{
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int filled = 0, fifo_available, i, retries;
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for (i=0; i<size/4; i++)
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{
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retries = 0;
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do
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{
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fifo_available = MMC_FIFO_DEPTH - MMC_GetWaterlevel(mmc_obj);
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if(retries++ > 10000)
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{
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rt_kprintf("ERROR: %s, get water level timeout\n", __func__);
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return -RT_ETIMEOUT;
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}
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}
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while(!fifo_available);
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SET_REG(mmc_obj->base + OFFSET_SDC_FIFO, *buf++);
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}
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retries = 0;
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while(MMC_IsDataStateBusy(mmc_obj))
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{
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if(retries++ > 10000)
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{
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rt_kprintf("ERROR: %s, timeout, data line keep being busy\n", __func__);
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return -RT_ETIMEOUT;
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}
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}
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return 0;
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}
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int MMC_ReadData(struct fh_mmc_obj *mmc_obj, rt_uint32_t *buf, rt_uint32_t size)
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{
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int fifo_available, i, retries;
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for (i=0; i<size/4; i++)
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{
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retries = 0;
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do
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{
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fifo_available = MMC_GetWaterlevel(mmc_obj);
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if(retries++ > 10000)
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{
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rt_kprintf("ERROR: %s, get water level timeout\n", __func__);
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return -RT_ETIMEOUT;
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}
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}
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while(!fifo_available);
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*buf++ = GET_REG(mmc_obj->base + OFFSET_SDC_FIFO);
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}
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retries = 0;
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while(MMC_IsDataStateBusy(mmc_obj))
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{
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if(retries++ > 10000)
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{
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rt_kprintf("ERROR: %s, timeout, data line keep being busy\n", __func__);
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return -RT_ETIMEOUT;
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}
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}
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return 0;
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}
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int MMC_UpdateClockRegister(struct fh_mmc_obj *mmc_obj, int div)
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{
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rt_uint32_t tick, timeout;
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tick = rt_tick_get();
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timeout = tick + RT_TICK_PER_SECOND / 10; //100ms in total
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/* disable clock */
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SET_REG(mmc_obj->base + OFFSET_SDC_CLKENA, 0);
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SET_REG(mmc_obj->base + OFFSET_SDC_CLKSRC, 0);
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/* inform CIU */
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SET_REG(mmc_obj->base + OFFSET_SDC_CMD, 1<<31 | 1<<21);
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while(GET_REG(mmc_obj->base + OFFSET_SDC_CMD) & 0x80000000)
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{
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tick = rt_tick_get();
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if(tick > timeout)
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{
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rt_kprintf("ERROR: %s, update clock timeout\n", __func__);
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return -RT_ETIMEOUT;
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}
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}
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/* set clock to desired speed */
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SET_REG(mmc_obj->base + OFFSET_SDC_CLKDIV, div);
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/* inform CIU */
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SET_REG(mmc_obj->base + OFFSET_SDC_CMD, 1<<31 | 1<<21);
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while(GET_REG(mmc_obj->base + OFFSET_SDC_CMD) & 0x80000000)
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{
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tick = rt_tick_get();
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if(tick > timeout)
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{
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rt_kprintf("ERROR: %s, update clock timeout\n", __func__);
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return -RT_ETIMEOUT;
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}
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}
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/* enable clock */
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SET_REG(mmc_obj->base + OFFSET_SDC_CLKENA, 1);
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/* inform CIU */
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SET_REG(mmc_obj->base + OFFSET_SDC_CMD, 1<<31 | 1<<21);
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while(GET_REG(mmc_obj->base + OFFSET_SDC_CMD) & 0x80000000)
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{
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tick = rt_tick_get();
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if(tick > timeout)
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{
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rt_kprintf("ERROR: %s, update clock timeout\n", __func__);
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return -RT_ETIMEOUT;
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}
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}
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return 0;
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}
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int MMC_SetCardWidth(struct fh_mmc_obj *mmc_obj, int width)
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{
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switch(width)
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{
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case MMC_CARD_WIDTH_1BIT:
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SET_REG(mmc_obj->base + OFFSET_SDC_CTYPE, 0);
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break;
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case MMC_CARD_WIDTH_4BIT:
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SET_REG(mmc_obj->base + OFFSET_SDC_CTYPE, 1);
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break;
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default:
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rt_kprintf("ERROR: %s, card width %d is not supported\n", __func__, width);
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return -RT_ERROR;
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break;
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}
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return 0;
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}
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int MMC_SendCommand(struct fh_mmc_obj *mmc_obj, rt_uint32_t cmd, rt_uint32_t arg, rt_uint32_t flags)
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{
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rt_uint32_t reg, tick, timeout;
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tick = rt_tick_get();
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timeout = tick + RT_TICK_PER_SECOND; //1s
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SET_REG(mmc_obj->base + OFFSET_SDC_CMDARG, arg);
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flags |= 1<<31 | 1<<29 | cmd;
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SET_REG(mmc_obj->base + OFFSET_SDC_CMD, flags);
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while(GET_REG(mmc_obj->base + OFFSET_SDC_CMD) & MMC_CMD_START_CMD)
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{
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tick = rt_tick_get();
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if(tick > timeout)
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{
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rt_kprintf("ERROR: %s, send cmd timeout\n", __func__);
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return -RT_ETIMEOUT;
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}
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}
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//fixme: check HLE_INT_STATUS
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return 0;
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}
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int MMC_ResetFifo(struct fh_mmc_obj *mmc_obj)
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{
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rt_uint32_t reg, tick, timeout;
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tick = rt_tick_get();
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timeout = tick + RT_TICK_PER_SECOND / 10; //100ms
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reg = GET_REG(mmc_obj->base + OFFSET_SDC_CTRL);
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reg |= 1 << 1;
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SET_REG(mmc_obj->base + OFFSET_SDC_CTRL, reg);
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//wait until fifo reset finish
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while(GET_REG(mmc_obj->base + OFFSET_SDC_CTRL) & MMC_CTRL_FIFO_RESET)
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{
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tick = rt_tick_get();
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if(tick > timeout)
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{
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rt_kprintf("ERROR: %s, FIFO reset timeout\n", __func__);
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return -RT_ETIMEOUT;
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}
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}
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return 0;
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}
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int MMC_Reset(struct fh_mmc_obj *mmc_obj)
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{
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rt_uint32_t reg, tick, timeout;
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tick = rt_tick_get();
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timeout = tick + RT_TICK_PER_SECOND / 10; //100ms
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reg = GET_REG(mmc_obj->base + OFFSET_SDC_BMOD);
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reg |= MMC_BMOD_RESET;
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SET_REG(mmc_obj->base + OFFSET_SDC_BMOD, reg);
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while(GET_REG(mmc_obj->base + OFFSET_SDC_BMOD) & MMC_BMOD_RESET)
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{
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tick = rt_tick_get();
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if(tick > timeout)
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{
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rt_kprintf("ERROR: %s, BMOD Software reset timeout\n", __func__);
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return -RT_ETIMEOUT;
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}
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}
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reg = GET_REG(mmc_obj->base + OFFSET_SDC_CTRL);
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reg |= MMC_CTRL_CONTROLLER_RESET | MMC_CTRL_FIFO_RESET | MMC_CTRL_DMA_RESET;
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SET_REG(mmc_obj->base + OFFSET_SDC_CTRL, reg);
|
||
|
|
|
||
|
|
tick = rt_tick_get();
|
||
|
|
timeout = tick + RT_TICK_PER_SECOND / 10; //100ms
|
||
|
|
while(GET_REG(mmc_obj->base + OFFSET_SDC_CTRL) & (MMC_CTRL_CONTROLLER_RESET | MMC_CTRL_FIFO_RESET | MMC_CTRL_DMA_RESET))
|
||
|
|
{
|
||
|
|
tick = rt_tick_get();
|
||
|
|
if(tick > timeout)
|
||
|
|
{
|
||
|
|
rt_kprintf("ERROR: %s, CTRL dma|fifo|ctrl reset timeout\n", __func__);
|
||
|
|
return -RT_ETIMEOUT;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
void MMC_Init(struct fh_mmc_obj *mmc_obj)
|
||
|
|
{
|
||
|
|
rt_uint32_t reg;
|
||
|
|
|
||
|
|
if(mmc_obj->mmc_reset)
|
||
|
|
mmc_obj->mmc_reset(mmc_obj);
|
||
|
|
|
||
|
|
MMC_Reset(mmc_obj);
|
||
|
|
|
||
|
|
//fixed burst
|
||
|
|
reg = GET_REG(mmc_obj->base + OFFSET_SDC_BMOD);
|
||
|
|
reg |= 1 << 1;
|
||
|
|
SET_REG(mmc_obj->base + OFFSET_SDC_BMOD, reg);
|
||
|
|
|
||
|
|
//fixme: power on ? ctrl by gpio ?
|
||
|
|
|
||
|
|
MMC_ClearRawInterrupt(mmc_obj, MMC_INT_STATUS_ALL);
|
||
|
|
MMC_SetInterruptMask(mmc_obj, 0x0);
|
||
|
|
|
||
|
|
//fixme: use_internal_dma
|
||
|
|
reg = GET_REG(mmc_obj->base + OFFSET_SDC_CTRL);
|
||
|
|
reg |= MMC_CTRL_INT_ENABLE;
|
||
|
|
#ifdef MMC_USE_DMA
|
||
|
|
reg |= MMC_CTRL_USE_DMA;
|
||
|
|
#endif
|
||
|
|
SET_REG(mmc_obj->base + OFFSET_SDC_CTRL, reg);
|
||
|
|
|
||
|
|
//set timeout param
|
||
|
|
SET_REG(mmc_obj->base + OFFSET_SDC_TMOUT, 0xffffffff);
|
||
|
|
|
||
|
|
//set fifo
|
||
|
|
reg = GET_REG(mmc_obj->base + OFFSET_SDC_FIFOTH);
|
||
|
|
reg = (reg >> 16) & 0x7ff;
|
||
|
|
reg = ((0x2 << 28) | ((reg/2) << 16) | ((reg/2 + 1) << 0));
|
||
|
|
SET_REG(mmc_obj->base + OFFSET_SDC_FIFOTH, reg);
|
||
|
|
}
|