273 lines
13 KiB
C
273 lines
13 KiB
C
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//*****************************************************************************
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//
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// hw_hibernate.h - Defines and Macros for the Hibernation module.
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//
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// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved.
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// Software License Agreement
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//
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// Texas Instruments (TI) is supplying this software for use solely and
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// exclusively on TI's microcontroller products. The software is owned by
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// TI and/or its suppliers, and is protected under applicable copyright
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// laws. You may not combine this software with "viral" open-source
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// software in order to form a larger program.
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//
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// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
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// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
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// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
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// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
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// DAMAGES, FOR ANY REASON WHATSOEVER.
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//
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// This is part of revision 8049 of the Stellaris Firmware Development Package.
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//
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//*****************************************************************************
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#ifndef __HW_HIBERNATE_H__
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#define __HW_HIBERNATE_H__
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//*****************************************************************************
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//
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// The following are defines for the Hibernation module register addresses.
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//
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//*****************************************************************************
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#define HIB_RTCC 0x400FC000 // Hibernation RTC Counter
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#define HIB_RTCM0 0x400FC004 // Hibernation RTC Match 0
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#define HIB_RTCM1 0x400FC008 // Hibernation RTC Match 1
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#define HIB_RTCLD 0x400FC00C // Hibernation RTC Load
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#define HIB_CTL 0x400FC010 // Hibernation Control
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#define HIB_IM 0x400FC014 // Hibernation Interrupt Mask
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#define HIB_RIS 0x400FC018 // Hibernation Raw Interrupt Status
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#define HIB_MIS 0x400FC01C // Hibernation Masked Interrupt
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// Status
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#define HIB_IC 0x400FC020 // Hibernation Interrupt Clear
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#define HIB_RTCT 0x400FC024 // Hibernation RTC Trim
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#define HIB_RTCSS 0x400FC028 // Hibernation RTC Sub Seconds
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#define HIB_DATA 0x400FC030 // Hibernation Data
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_RTCC register.
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//
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//*****************************************************************************
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#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter
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#define HIB_RTCC_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_RTCM0 register.
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//
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//*****************************************************************************
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#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0
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#define HIB_RTCM0_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_RTCM1 register.
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//
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//*****************************************************************************
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#define HIB_RTCM1_M 0xFFFFFFFF // RTC Match 1
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#define HIB_RTCM1_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_RTCLD register.
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//
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//*****************************************************************************
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#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load
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#define HIB_RTCLD_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_CTL register.
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//
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//*****************************************************************************
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#define HIB_CTL_WRC 0x80000000 // Write Complete/Capable
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#define HIB_CTL_OSCHYS 0x00040000 // 32
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#define HIB_CTL_OSCDRV 0x00020000 // Oscillator Drive Capability
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#define HIB_CTL_OSCBYP 0x00010000 // Oscillator Bypass
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#define HIB_CTL_VBATSEL_M 0x00006000 // Select for Low-Battery
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// Comparator
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#define HIB_CTL_VBATSEL_1_9V 0x00000000 // 1.9 Volts
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#define HIB_CTL_VBATSEL_2_1V 0x00002000 // 2.1 Volts (default)
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#define HIB_CTL_VBATSEL_2_3V 0x00004000 // 2.3 Volts
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#define HIB_CTL_VBATSEL_2_5V 0x00006000 // 2.5 Volts
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#define HIB_CTL_BATCHK 0x00000400 // Check Battery Status
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#define HIB_CTL_BATWKEN 0x00000200 // Wake on Low Battery
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#define HIB_CTL_VDD3ON 0x00000100 // VDD Powered
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#define HIB_CTL_VABORT 0x00000080 // Power Cut Abort Enable
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#define HIB_CTL_CLK32EN 0x00000040 // Clocking Enable
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#define HIB_CTL_LOWBATEN 0x00000020 // Low Battery Monitoring Enable
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#define HIB_CTL_PINWEN 0x00000010 // External WAKE Pin Enable
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#define HIB_CTL_RTCWEN 0x00000008 // RTC Wake-up Enable
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#define HIB_CTL_CLKSEL 0x00000004 // Hibernation Module Clock Select
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#define HIB_CTL_HIBREQ 0x00000002 // Hibernation Request
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#define HIB_CTL_RTCEN 0x00000001 // RTC Timer Enable
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_IM register.
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//
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//*****************************************************************************
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#define HIB_IM_WC 0x00000010 // External Write Complete/Capable
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// Interrupt Mask
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#define HIB_IM_EXTW 0x00000008 // External Wake-Up Interrupt Mask
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#define HIB_IM_LOWBAT 0x00000004 // Low Battery Voltage Interrupt
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// Mask
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#define HIB_IM_RTCALT1 0x00000002 // RTC Alert 1 Interrupt Mask
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#define HIB_IM_RTCALT0 0x00000001 // RTC Alert 0 Interrupt Mask
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_RIS register.
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//
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//*****************************************************************************
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#define HIB_RIS_WC 0x00000010 // Write Complete/Capable Raw
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// Interrupt Status
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#define HIB_RIS_EXTW 0x00000008 // External Wake-Up Raw Interrupt
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// Status
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#define HIB_RIS_LOWBAT 0x00000004 // Low Battery Voltage Raw
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// Interrupt Status
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#define HIB_RIS_RTCALT1 0x00000002 // RTC Alert 1 Raw Interrupt Status
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#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert 0 Raw Interrupt Status
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_MIS register.
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//
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//*****************************************************************************
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#define HIB_MIS_WC 0x00000010 // Write Complete/Capable Masked
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// Interrupt Status
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#define HIB_MIS_EXTW 0x00000008 // External Wake-Up Masked
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// Interrupt Status
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#define HIB_MIS_LOWBAT 0x00000004 // Low Battery Voltage Masked
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// Interrupt Status
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#define HIB_MIS_RTCALT1 0x00000002 // RTC Alert 1 Masked Interrupt
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// Status
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#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert 0 Masked Interrupt
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// Status
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_IC register.
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//
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//*****************************************************************************
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#define HIB_IC_WC 0x00000010 // Write Complete/Capable Masked
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// Interrupt Clear
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#define HIB_IC_EXTW 0x00000008 // External Wake-Up Masked
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// Interrupt Clear
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#define HIB_IC_LOWBAT 0x00000004 // Low Battery Voltage Masked
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// Interrupt Clear
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#define HIB_IC_RTCALT1 0x00000002 // RTC Alert1 Masked Interrupt
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// Clear
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#define HIB_IC_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt
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// Clear
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_RTCT register.
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//
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//*****************************************************************************
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#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value
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#define HIB_RTCT_TRIM_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_RTCSS register.
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//
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//*****************************************************************************
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#define HIB_RTCSS_RTCSSM_M 0x7FFF0000 // RTC Sub Seconds Match
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#define HIB_RTCSS_RTCSSC_M 0x00007FFF // RTC Sub Seconds Count
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#define HIB_RTCSS_RTCSSM_S 16
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#define HIB_RTCSS_RTCSSC_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_DATA register.
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//
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//*****************************************************************************
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#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV Data
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#define HIB_DATA_RTD_S 0
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//*****************************************************************************
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//
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// The following definitions are deprecated.
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//
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//*****************************************************************************
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#ifndef DEPRECATED
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//*****************************************************************************
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//
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// The following are deprecated defines for the Hibernation module register
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// addresses.
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//
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//*****************************************************************************
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#define HIB_DATA_END 0x400FC130 // end of data area, exclusive
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//*****************************************************************************
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//
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// The following are deprecated defines for the bit fields in the HIB_RTCC
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// register.
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//
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//*****************************************************************************
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#define HIB_RTCC_MASK 0xFFFFFFFF // RTC counter mask
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//*****************************************************************************
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//
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// The following are deprecated defines for the bit fields in the HIB_RTCM0
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// register.
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//
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//*****************************************************************************
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#define HIB_RTCM0_MASK 0xFFFFFFFF // RTC match 0 mask
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//*****************************************************************************
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//
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// The following are deprecated defines for the bit fields in the HIB_RTCM1
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// register.
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//
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//*****************************************************************************
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#define HIB_RTCM1_MASK 0xFFFFFFFF // RTC match 1 mask
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//*****************************************************************************
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//
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// The following are deprecated defines for the bit fields in the HIB_RTCLD
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// register.
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//
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//*****************************************************************************
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#define HIB_RTCLD_MASK 0xFFFFFFFF // RTC load mask
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//*****************************************************************************
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//
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// The following are deprecated defines for the bit fields in the HIB_RIS
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// register.
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//
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//*****************************************************************************
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#define HIB_RID_RTCALT0 0x00000001 // RTC match 0 interrupt
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//*****************************************************************************
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//
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// The following are deprecated defines for the bit fields in the HIB_MIS
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// register.
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//
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//*****************************************************************************
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#define HIB_MID_RTCALT0 0x00000001 // RTC match 0 interrupt
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//*****************************************************************************
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//
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// The following are deprecated defines for the bit fields in the HIB_RTCT
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// register.
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//
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//*****************************************************************************
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#define HIB_RTCT_MASK 0x0000FFFF // RTC trim mask
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//*****************************************************************************
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//
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// The following are deprecated defines for the bit fields in the HIB_DATA
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// register.
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//
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//*****************************************************************************
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#define HIB_DATA_MASK 0xFFFFFFFF // NV memory data mask
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#endif
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#endif // __HW_HIBERNATE_H__
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