308 lines
13 KiB
C
308 lines
13 KiB
C
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#ifndef _UART_HW_H_
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#define _UART_HW_H_
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#include <stdint.h>
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/** @name Register Map
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*
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* Registers of the UART.
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* @{
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*/
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typedef struct
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{
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volatile uint32_t CR; /**< Control Register */
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volatile uint32_t MR; /**< Mode Register */
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volatile uint32_t IER; /**< Interrupt Enable */
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volatile uint32_t IDR; /**< Interrupt Disable */
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volatile uint32_t IMR; /**< Interrupt Mask */
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volatile uint32_t ISR; /**< Interrupt Status */
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volatile uint32_t BAUDGEN; /**< Baud Rate Generator */
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volatile uint32_t RXTOUT; /**< RX Timeout */
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volatile uint32_t RXWM; /**< RX FIFO Trigger Level */
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volatile uint32_t MODEMCR; /**< Modem Control */
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volatile uint32_t MODEMSR; /**< Modem Status */
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volatile uint32_t SR; /**< Channel Status */
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volatile uint32_t FIFO; /**< FIFO */
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volatile uint32_t BAUDDIV; /**< Baud Rate Divider */
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volatile uint32_t FLOWDEL; /**< Flow Delay */
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volatile uint32_t RESERVED1;
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volatile uint32_t RESERVED2;
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volatile uint32_t TXWM; /* TX FIFO Trigger Level */
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} UART_Registers;
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/* @} */
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/** @name Control Register
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*
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* The Control register (CR) controls the major functions of the device.
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*
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* Control Register Bit Definition
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*/
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#define UART_CR_STOPBRK 0x00000100 /**< Stop transmission of break */
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#define UART_CR_STARTBRK 0x00000080 /**< Set break */
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#define UART_CR_TORST 0x00000040 /**< RX timeout counter restart */
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#define UART_CR_TX_DIS 0x00000020 /**< TX disabled. */
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#define UART_CR_TX_EN 0x00000010 /**< TX enabled */
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#define UART_CR_RX_DIS 0x00000008 /**< RX disabled. */
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#define UART_CR_RX_EN 0x00000004 /**< RX enabled */
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#define UART_CR_EN_DIS_MASK 0x0000003C /**< Enable/disable Mask */
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#define UART_CR_TXRST 0x00000002 /**< TX logic reset */
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#define UART_CR_RXRST 0x00000001 /**< RX logic reset */
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/* @}*/
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/** @name Mode Register
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*
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* The mode register (MR) defines the mode of transfer as well as the data
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* format. If this register is modified during transmission or reception,
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* data validity cannot be guaranteed.
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*
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* Mode Register Bit Definition
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* @{
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*/
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#define UART_MR_CCLK 0x00000400 /**< Input clock selection */
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#define UART_MR_CHMODE_R_LOOP 0x00000300 /**< Remote loopback mode */
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#define UART_MR_CHMODE_L_LOOP 0x00000200 /**< Local loopback mode */
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#define UART_MR_CHMODE_ECHO 0x00000100 /**< Auto echo mode */
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#define UART_MR_CHMODE_NORM 0x00000000 /**< Normal mode */
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#define UART_MR_CHMODE_SHIFT 8 /**< Mode shift */
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#define UART_MR_CHMODE_MASK 0x00000300 /**< Mode mask */
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#define UART_MR_STOPMODE_2_BIT 0x00000080 /**< 2 stop bits */
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#define UART_MR_STOPMODE_1_5_BIT 0x00000040 /**< 1.5 stop bits */
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#define UART_MR_STOPMODE_1_BIT 0x00000000 /**< 1 stop bit */
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#define UART_MR_STOPMODE_SHIFT 6 /**< Stop bits shift */
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#define UART_MR_STOPMODE_MASK 0x000000A0 /**< Stop bits mask */
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#define UART_MR_PARITY_NONE 0x00000020 /**< No parity mode */
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#define UART_MR_PARITY_MARK 0x00000018 /**< Mark parity mode */
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#define UART_MR_PARITY_SPACE 0x00000010 /**< Space parity mode */
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#define UART_MR_PARITY_ODD 0x00000008 /**< Odd parity mode */
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#define UART_MR_PARITY_EVEN 0x00000000 /**< Even parity mode */
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#define UART_MR_PARITY_SHIFT 3 /**< Parity setting shift */
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#define UART_MR_PARITY_MASK 0x00000038 /**< Parity mask */
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#define UART_MR_CHARLEN_6_BIT 0x00000006 /**< 6 bits data */
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#define UART_MR_CHARLEN_7_BIT 0x00000004 /**< 7 bits data */
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#define UART_MR_CHARLEN_8_BIT 0x00000000 /**< 8 bits data */
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#define UART_MR_CHARLEN_SHIFT 1 /**< Data Length shift */
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#define UART_MR_CHARLEN_MASK 0x00000006 /**< Data length mask */
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#define UART_MR_CLKSEL 0x00000001 /**< Input clock selection */
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/* @} */
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/** @name Interrupt Registers
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*
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* Interrupt control logic uses the interrupt enable register (IER) and the
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* interrupt disable register (IDR) to set the value of the bits in the
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* interrupt mask register (IMR). The IMR determines whether to pass an
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* interrupt to the interrupt status register (ISR).
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* Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
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* interrupt. IMR and ISR are read only, and IER and IDR are write only.
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* Reading either IER or IDR returns 0x00.
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*
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* All four registers have the same bit definitions.
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*
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* @{
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*/
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#define UART_IXR_DMS 0x00000200 /**< Modem status change interrupt */
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#define UART_IXR_TOUT 0x00000100 /**< Timeout error interrupt */
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#define UART_IXR_PARITY 0x00000080 /**< Parity error interrupt */
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#define UART_IXR_FRAMING 0x00000040 /**< Framing error interrupt */
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#define UART_IXR_OVER 0x00000020 /**< Overrun error interrupt */
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#define UART_IXR_TXFULL 0x00000010 /**< TX FIFO full interrupt. */
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#define UART_IXR_TXEMPTY 0x00000008 /**< TX FIFO empty interrupt. */
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#define UART_IXR_RXFULL 0x00000004 /**< RX FIFO full interrupt. */
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#define UART_IXR_RXEMPTY 0x00000002 /**< RX FIFO empty interrupt. */
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#define UART_IXR_RXOVR 0x00000001 /**< RX FIFO trigger interrupt. */
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#define UART_IXR_MASK 0x000003FF /**< Valid bit mask */
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/* @} */
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/** @name Baud Rate Generator Register
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*
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* The baud rate generator control register (BRGR) is a 16 bit register that
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* controls the receiver bit sample clock and baud rate.
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* Valid values are 1 - 65535.
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*
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* Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit
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* in the MR register.
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* @{
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*/
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#define UART_BAUDGEN_DISABLE 0x00000000 /**< Disable clock */
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#define UART_BAUDGEN_MASK 0x0000FFFF /**< Valid bits mask */
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/* @} */
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/** @name Baud Divisor Rate register
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*
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* The baud rate divider register (BDIV) controls how much the bit sample
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* rate is divided by. It sets the baud rate.
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* Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored.
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*
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* Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by
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* the MR_CCLK bit in the MR register.
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* @{
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*/
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#define UART_BAUDDIV_MASK 0x000000FF /**< 8 bit baud divider mask */
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/* @} */
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/*
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Page 496
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Simplifyed Table 19-1 UART Parameter Value Examples
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Parameter Value Examples
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Clock Baud BRGR-CD BDIV-CD Actual Baud Rate
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UART Ref clock 600 10417 7
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UART Ref clock 9,600 651 7
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UART Ref clock 28,800 347 4
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UART Ref clock 115,200 62 6
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UART Ref clock 230,400 31 6
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*/
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/*Baudrates assuming input clock speed is 3125000L */
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/*Baud_rate_gen_reg0*/
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#define UART_BAUDGEN_115200 62 /*Baud Rate Clock Divisor*/
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/*Register Baud_rate_divider_reg0 Details*/
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#define UART_BAUDDIV_115200 6 /*Baud Rate Clock Divisor*/
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/** @name Receiver Timeout Register
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*
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* Use the receiver timeout register (RTR) to detect an idle condition on
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* the receiver data line.
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*
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* @{
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*/
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#define UART_RXTOUT_DISABLE 0x00000000 /**< Disable time out */
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#define UART_RXTOUT_MASK 0x000000FF /**< Valid bits mask */
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/* @} */
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/** @name Receiver FIFO Trigger Level Register
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*
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* Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at
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* which the RX FIFO triggers an interrupt event.
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* @{
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*/
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#define UART_RXWM_DISABLE 0x00000000 /**< Disable RX trigger interrupt */
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#define UART_RXWM_MASK 0x0000003F /**< Valid bits mask */
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/* @} */
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/** @name Modem Control Register
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*
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* This register (MODEMCR) controls the interface with the modem or data set,
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* or a peripheral device emulating a modem.
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*
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* @{
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*/
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#define UART_MODEMCR_FCM 0x00000010 /**< Flow control mode */
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#define UART_MODEMCR_RTS 0x00000002 /**< Request to send */
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#define UART_MODEMCR_DTR 0x00000001 /**< Data terminal ready */
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/* @} */
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/** @name Modem Status Register
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*
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* This register (MODEMSR) indicates the current state of the control lines
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* from a modem, or another peripheral device, to the CPU. In addition, four
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* bits of the modem status register provide change information. These bits
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* are set to a logic 1 whenever a control input from the modem changes state.
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*
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* Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem
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* status interrupt is generated and this is reflected in the modem status
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* register.
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*
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* @{
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*/
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#define UART_MODEMSR_FCMS 0x00000100 /**< Flow control mode (FCMS) */
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#define UART_MODEMSR_DCD 0x00000080 /**< Complement of DCD input */
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#define UART_MODEMSR_RI 0x00000040 /**< Complement of RI input */
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#define UART_MODEMSR_DSR 0x00000020 /**< Complement of DSR input */
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#define UART_MODEMSR_CTS 0x00000010 /**< Complement of CTS input */
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#define UART_MEDEMSR_DCDX 0x00000008 /**< Delta DCD indicator */
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#define UART_MEDEMSR_RIX 0x00000004 /**< Change of RI */
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#define UART_MEDEMSR_DSRX 0x00000002 /**< Change of DSR */
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#define UART_MEDEMSR_CTSX 0x00000001 /**< Change of CTS */
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/* @} */
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/** @name Channel Status Register
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*
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* The channel status register (CSR) is provided to enable the control logic
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* to monitor the status of bits in the channel interrupt status register,
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* even if these are masked out by the interrupt mask register.
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*
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* @{
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*/
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#define UART_SR_FLOWDEL 0x00001000 /**< RX FIFO fill over flow delay */
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#define UART_SR_TACTIVE 0x00000800 /**< TX active */
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#define UART_SR_RACTIVE 0x00000400 /**< RX active */
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#define UART_SR_DMS 0x00000200 /**< Delta modem status change */
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#define UART_SR_TOUT 0x00000100 /**< RX timeout */
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#define UART_SR_PARITY 0x00000080 /**< RX parity error */
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#define UART_SR_FRAME 0x00000040 /**< RX frame error */
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#define UART_SR_OVER 0x00000020 /**< RX overflow error */
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#define UART_SR_TXFULL 0x00000010 /**< TX FIFO full */
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#define UART_SR_TXEMPTY 0x00000008 /**< TX FIFO empty */
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#define UART_SR_RXFULL 0x00000004 /**< RX FIFO full */
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#define UART_SR_RXEMPTY 0x00000002 /**< RX FIFO empty */
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#define UART_SR_RXOVR 0x00000001 /**< RX FIFO fill over trigger */
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/* @} */
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/** @name Flow Delay Register
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*
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* Operation of the flow delay register (FLOWDEL) is very similar to the
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* receive FIFO trigger register. An internal trigger signal activates when the
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* FIFO is filled to the level set by this register. This trigger will not
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* cause an interrupt, although it can be read through the channel status
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* register. In hardware flow control mode, RTS is deactivated when the trigger
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* becomes active. RTS only resets when the FIFO level is four less than the
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* level of the flow delay trigger and the flow delay trigger is not activated.
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* A value less than 4 disables the flow delay.
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* @{
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*/
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#define UART_FLOWDEL_MASK UART_RXWM_MASK /**< Valid bit mask */
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/* @} */
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/** @name Base Address of UART0
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*
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* The base address of UART0
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*/
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#define UART0_BASE 0xE0000000
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/** @name Base Address of UART1
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*
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* The base address of UART1
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*/
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#define UART1_BASE 0xE0001000
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#define UART0 ((UART_Registers*)UART0_BASE)
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#define UART1 ((UART_Registers*)UART1_BASE)
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/****************************************************************************/
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/**
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* Determine if there is receive data in the receiver and/or FIFO.
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*
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* @param BaseAddress contains the base address of the device.
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*
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* @return TRUE if there is receive data, FALSE otherwise.
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*
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* @note C-Style signature:
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* uint32_t UartDataReceived(uint32_t BaseAddress)
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*
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******************************************************************************/
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#define UartDataReceived(BaseAddress) \
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!((io_in32((BaseAddress) + UART_SR_OFFSET) & \
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UART_SR_RXEMPTY) == UART_SR_RXEMPTY)
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/****************************************************************************/
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/**
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* Determine if a byte of data can be sent with the transmitter.
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*
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* @param BaseAddress contains the base address of the device.
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*
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* @return TRUE if the TX FIFO is full, FALSE if a byte can be put in the
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* FIFO.
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*
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* @note C-Style signature:
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* uint32_t UartTXFIFOFull(uint32_t BaseAddress)
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*
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******************************************************************************/
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#define UartTXFIFOFull(BaseAddress) \
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((io_in32((BaseAddress) + UART_SR_OFFSET) & \
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UART_SR_TXFULL) == UART_SR_TXFULL)
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#endif
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