427 lines
8.3 KiB
C
427 lines
8.3 KiB
C
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#include "nds32.h"
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.set regno, 0
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#ifdef __TARGET_IFC_EXT
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.set regno, regno+1
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#endif
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#ifdef __TARGET_ZOL_EXT
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.set regno, regno+3
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#endif
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/* Descend PSW.INTL and enable PSW.AEN */
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.macro IntlDescend
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mfsr $r1, $PSW
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#ifdef __TARGET_ZOL_EXT
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/* Also enable ZOL (PSW.AEN) */
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xori $r1, $r1, #((1 << 13) | (1 << 1))
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#else
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addi $r1, $r1, #-2
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#endif
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mtsr $r1, $PSW
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.endm
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/* FPU registers */
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.macro SAVE_FPU_REGS_00
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fsdi.bi $fd3, [$sp], -8
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fsdi.bi $fd2, [$sp], -8
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fsdi.bi $fd1, [$sp], -8
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fsdi $fd0, [$sp+0]
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.endm
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.macro SAVE_FPU_REGS_01
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fsdi.bi $fd7, [$sp], -8
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fsdi.bi $fd6, [$sp], -8
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fsdi.bi $fd5, [$sp], -8
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fsdi.bi $fd4, [$sp], -8
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SAVE_FPU_REGS_00
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.endm
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.macro SAVE_FPU_REGS_02
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fsdi.bi $fd15, [$sp], -8
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fsdi.bi $fd14, [$sp], -8
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fsdi.bi $fd13, [$sp], -8
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fsdi.bi $fd12, [$sp], -8
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fsdi.bi $fd11, [$sp], -8
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fsdi.bi $fd10, [$sp], -8
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fsdi.bi $fd9, [$sp], -8
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fsdi.bi $fd8, [$sp], -8
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SAVE_FPU_REGS_01
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.endm
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.macro SAVE_FPU_REGS_03
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fsdi.bi $fd31, [$sp], -8
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fsdi.bi $fd30, [$sp], -8
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fsdi.bi $fd29, [$sp], -8
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fsdi.bi $fd28, [$sp], -8
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fsdi.bi $fd27, [$sp], -8
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fsdi.bi $fd26, [$sp], -8
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fsdi.bi $fd25, [$sp], -8
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fsdi.bi $fd24, [$sp], -8
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fsdi.bi $fd23, [$sp], -8
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fsdi.bi $fd22, [$sp], -8
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fsdi.bi $fd21, [$sp], -8
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fsdi.bi $fd20, [$sp], -8
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fsdi.bi $fd19, [$sp], -8
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fsdi.bi $fd18, [$sp], -8
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fsdi.bi $fd17, [$sp], -8
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fsdi.bi $fd16, [$sp], -8
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SAVE_FPU_REGS_02
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.endm
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.macro push_fpu
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#if defined(__NDS32_EXT_FPU_CONFIG_0__)
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addi $sp, $sp, -8
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SAVE_FPU_REGS_00
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#elif defined(__NDS32_EXT_FPU_CONFIG_1__)
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addi $sp, $sp, -8
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SAVE_FPU_REGS_01
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#elif defined(__NDS32_EXT_FPU_CONFIG_2__)
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addi $sp, $sp, -8
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SAVE_FPU_REGS_02
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#elif defined(__NDS32_EXT_FPU_CONFIG_3__)
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addi $sp, $sp, -8
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SAVE_FPU_REGS_03
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#else
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#endif
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.endm
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.macro RESTORE_FPU_REGS_00
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fldi.bi $fd0, [$sp], 8
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fldi.bi $fd1, [$sp], 8
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fldi.bi $fd2, [$sp], 8
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fldi.bi $fd3, [$sp], 8
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.endm
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.macro RESTORE_FPU_REGS_01
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RESTORE_FPU_REGS_00
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fldi.bi $fd4, [$sp], 8
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fldi.bi $fd5, [$sp], 8
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fldi.bi $fd6, [$sp], 8
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fldi.bi $fd7, [$sp], 8
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.endm
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.macro RESTORE_FPU_REGS_02
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RESTORE_FPU_REGS_01
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fldi.bi $fd8, [$sp], 8
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fldi.bi $fd9, [$sp], 8
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fldi.bi $fd10, [$sp], 8
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fldi.bi $fd11, [$sp], 8
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fldi.bi $fd12, [$sp], 8
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fldi.bi $fd13, [$sp], 8
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fldi.bi $fd14, [$sp], 8
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fldi.bi $fd15, [$sp], 8
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.endm
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.macro RESTORE_FPU_REGS_03
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RESTORE_FPU_REGS_02
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fldi.bi $fd16, [$sp], 8
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fldi.bi $fd17, [$sp], 8
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fldi.bi $fd18, [$sp], 8
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fldi.bi $fd19, [$sp], 8
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fldi.bi $fd20, [$sp], 8
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fldi.bi $fd21, [$sp], 8
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fldi.bi $fd22, [$sp], 8
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fldi.bi $fd23, [$sp], 8
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fldi.bi $fd24, [$sp], 8
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fldi.bi $fd25, [$sp], 8
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fldi.bi $fd26, [$sp], 8
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fldi.bi $fd27, [$sp], 8
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fldi.bi $fd28, [$sp], 8
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fldi.bi $fd29, [$sp], 8
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fldi.bi $fd30, [$sp], 8
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fldi.bi $fd31, [$sp], 8
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.endm
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.macro pop_fpu
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#if defined(__NDS32_EXT_FPU_CONFIG_0__)
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RESTORE_FPU_REGS_00
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#elif defined(__NDS32_EXT_FPU_CONFIG_1__)
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RESTORE_FPU_REGS_01
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#elif defined(__NDS32_EXT_FPU_CONFIG_2__)
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RESTORE_FPU_REGS_02
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#elif defined(__NDS32_EXT_FPU_CONFIG_3__)
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RESTORE_FPU_REGS_03
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#else
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#endif
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.endm
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/* FPU Caller registers */
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.macro SAVE_FPU_CALLER_REGS_00
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addi $sp, $sp, -8
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fsdi.bi $fd2, [$sp], -8
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fsdi.bi $fd1, [$sp], -8
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fsdi $fd0, [$sp+0]
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.endm
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.macro SAVE_FPU_CALLER_REGS_01
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SAVE_FPU_CALLER_REGS_00
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.endm
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.macro SAVE_FPU_CALLER_REGS_02
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addi $sp, $sp, -8
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fsdi.bi $fd15, [$sp], -8
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fsdi.bi $fd14, [$sp], -8
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fsdi.bi $fd13, [$sp], -8
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fsdi.bi $fd12, [$sp], -8
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fsdi.bi $fd11, [$sp], -8
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fsdi.bi $fd2, [$sp], -8
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fsdi.bi $fd1, [$sp], -8
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fsdi $fd0, [$sp+0]
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.endm
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.macro SAVE_FPU_CALLER_REGS_03
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addi $sp, $sp, -8
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fsdi.bi $fd23, [$sp], -8
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fsdi.bi $fd22, [$sp], -8
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fsdi.bi $fd21, [$sp], -8
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fsdi.bi $fd20, [$sp], -8
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fsdi.bi $fd19, [$sp], -8
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fsdi.bi $fd18, [$sp], -8
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fsdi.bi $fd17, [$sp], -8
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fsdi.bi $fd16, [$sp], -8
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fsdi.bi $fd15, [$sp], -8
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fsdi.bi $fd14, [$sp], -8
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fsdi.bi $fd13, [$sp], -8
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fsdi.bi $fd12, [$sp], -8
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fsdi.bi $fd11, [$sp], -8
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fsdi.bi $fd2, [$sp], -8
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fsdi.bi $fd1, [$sp], -8
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fsdi $fd0, [$sp+0]
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.endm
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.macro push_fpu_caller
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#if defined(__NDS32_EXT_FPU_CONFIG_0__)
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SAVE_FPU_CALLER_REGS_00
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#elif defined(__NDS32_EXT_FPU_CONFIG_1__)
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SAVE_FPU_CALLER_REGS_01
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#elif defined(__NDS32_EXT_FPU_CONFIG_2__)
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SAVE_FPU_CALLER_REGS_02
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#elif defined(__NDS32_EXT_FPU_CONFIG_3__)
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SAVE_FPU_CALLER_REGS_03
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#else
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#endif
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.endm
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.macro RESTORE_FPU_CALLER_REGS_00
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fldi.bi $fd0, [$sp], 8
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fldi.bi $fd1, [$sp], 8
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fldi.bi $fd2, [$sp], 8
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.endm
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.macro RESTORE_FPU_CALLER_REGS_01
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RESTORE_FPU_CALLER_REGS_00
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.endm
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.macro RESTORE_FPU_CALLER_REGS_02
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fldi.bi $fd0, [$sp], 8
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fldi.bi $fd1, [$sp], 8
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fldi.bi $fd2, [$sp], 8
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fldi.bi $fd11, [$sp], 8
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fldi.bi $fd12, [$sp], 8
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fldi.bi $fd13, [$sp], 8
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fldi.bi $fd14, [$sp], 8
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fldi.bi $fd15, [$sp], 8
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.endm
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.macro RESTORE_FPU_CALLER_REGS_03
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fldi.bi $fd0, [$sp], 8
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fldi.bi $fd1, [$sp], 8
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fldi.bi $fd2, [$sp], 8
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fldi.bi $fd11, [$sp], 8
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fldi.bi $fd12, [$sp], 8
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fldi.bi $fd13, [$sp], 8
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fldi.bi $fd14, [$sp], 8
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fldi.bi $fd15, [$sp], 8
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fldi.bi $fd16, [$sp], 8
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fldi.bi $fd17, [$sp], 8
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fldi.bi $fd18, [$sp], 8
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fldi.bi $fd19, [$sp], 8
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fldi.bi $fd20, [$sp], 8
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fldi.bi $fd21, [$sp], 8
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fldi.bi $fd22, [$sp], 8
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fldi.bi $fd23, [$sp], 8
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.endm
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.macro pop_fpu_caller
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#if defined(__NDS32_EXT_FPU_CONFIG_0__)
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RESTORE_FPU_CALLER_REGS_00
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#elif defined(__NDS32_EXT_FPU_CONFIG_1__)
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RESTORE_FPU_CALLER_REGS_01
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#elif defined(__NDS32_EXT_FPU_CONFIG_2__)
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RESTORE_FPU_CALLER_REGS_02
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#elif defined(__NDS32_EXT_FPU_CONFIG_3__)
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RESTORE_FPU_CALLER_REGS_03
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#else
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#endif
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.endm
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/* IFC system register */
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.macro MFUSR_IFC R0="$r1"
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mfusr \R0, $IFC_LP
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.endm
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.macro MTUSR_IFC R0="$r1"
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mtusr \R0, $IFC_LP
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.endm
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/* ZOL system registers */
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.macro MFUSR_ZOL R0="$r1", R1="$r2", R2="$r3"
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mfusr \R0, $LB
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mfusr \R1, $LE
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mfusr \R2, $LC
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.endm
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.macro MTUSR_ZOL R0="$r1", R1="$r2", R2="$r3"
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mtusr \R0, $LB
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mtusr \R1, $LE
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mtusr \R2, $LC
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.endm
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/* Context-switch save and restore routines */
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.macro SAVE_ALL
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pushm $r6, $r30
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mfsr $r1, $IPC
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mfsr $r2, $IPSW
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.if (regno == 4)
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MFUSR_ZOL "$r3","$r4","$r5"
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MFUSR_IFC "$r6"
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pushm $r0, $r6 /* $0 is dummy */
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.else
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.if (regno == 3)
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MFUSR_ZOL "$r3","$r4","$r5"
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pushm $r1, $r5
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.else
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.if (regno == 1)
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MFUSR_IFC "$r3"
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pushm $r1, $r3
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.else
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pushm $r1, $r2
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.endif
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.endif
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.endif
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push_fpu
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.endm
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.macro RESTORE_ALL
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pop_fpu
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setgie.d
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dsb
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.if (regno == 4)
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popm $r0, $r6 /* $0 is dummy */
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MTUSR_ZOL "$r3","$r4","$r5"
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MTUSR_IFC "$r6"
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.else
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.if (regno == 3)
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popm $r1, $r5
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MTUSR_ZOL "$r3","$r4","$r5"
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.else
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.if (regno == 1)
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popm $r1, $r3
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MTUSR_IFC "$r3"
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.else
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popm $r1, $r2
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.endif
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.endif
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.endif
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mtsr $r1, $IPC
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mtsr $r2, $IPSW
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popm $r6, $r30
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popm $r0, $r5
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.endm
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/* Nested IRQ save and restore routines*/
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.macro SAVE_CALLER
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pushm $r15,$r30 /* full: 16 gpr, reduce: 4 gpr */
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.if (regno == 4)
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MFUSR_ZOL "$r1","$r2","$r3"
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MFUSR_IFC "$r4"
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pushm $r1, $r4
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mfsr $r1, $IPC
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mfsr $r2, $IPSW
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pushm $r1, $r2
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.else
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mfsr $r1, $IPC
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mfsr $r2, $IPSW
|
||
|
|
.if (regno == 3)
|
||
|
|
MFUSR_ZOL "$r3","$r4","$r5"
|
||
|
|
pushm $r0, $r5 /* $0 is dummy */
|
||
|
|
.else
|
||
|
|
.if (regno == 1)
|
||
|
|
MFUSR_IFC "$r3"
|
||
|
|
pushm $r0, $r3 /* $r0 is dummy */
|
||
|
|
.else
|
||
|
|
pushm $r1, $r2
|
||
|
|
.endif
|
||
|
|
.endif
|
||
|
|
.endif
|
||
|
|
|
||
|
|
push_fpu_caller
|
||
|
|
.endm
|
||
|
|
|
||
|
|
.macro RESTORE_CALLER
|
||
|
|
pop_fpu_caller
|
||
|
|
setgie.d
|
||
|
|
dsb
|
||
|
|
|
||
|
|
.if (regno == 4)
|
||
|
|
popm $r1, $r2
|
||
|
|
mtsr $r1, $IPC
|
||
|
|
mtsr $r2, $IPSW
|
||
|
|
|
||
|
|
popm $r1, $r4
|
||
|
|
MTUSR_ZOL "$r1","$r2","$r3"
|
||
|
|
MTUSR_IFC "$r4"
|
||
|
|
.else
|
||
|
|
.if (regno == 3)
|
||
|
|
popm $r0, $r5 /* $0 is dummy */
|
||
|
|
MTUSR_ZOL "$r3","$r4","$r5"
|
||
|
|
.else
|
||
|
|
.if (regno == 1)
|
||
|
|
popm $r0, $r3 /* $0 is dummy */
|
||
|
|
MTUSR_IFC "$r3"
|
||
|
|
.else
|
||
|
|
popm $r1, $r2
|
||
|
|
.endif
|
||
|
|
.endif
|
||
|
|
mtsr $r1, $IPC
|
||
|
|
mtsr $r2, $IPSW
|
||
|
|
.endif
|
||
|
|
|
||
|
|
popm $r15,$r30 /* full: 16 gpr, reduce: 4 gpr*/
|
||
|
|
popm $r0, $r5
|
||
|
|
.endm
|
||
|
|
|
||
|
|
/* Non-Nested IRQ save and restore routines */
|
||
|
|
.macro SAVE_CALLER_UNNESTED
|
||
|
|
pushm $r15,$r30 /* full: 16 gpr, reduce: 4 gpr */
|
||
|
|
|
||
|
|
.if (regno == 1)
|
||
|
|
MFUSR_IFC "$r1"
|
||
|
|
pushm $r0, $r1 /* $r0 is dummy */
|
||
|
|
.endif
|
||
|
|
|
||
|
|
push_fpu_caller
|
||
|
|
.endm
|
||
|
|
|
||
|
|
.macro RESTORE_CALLER_UNNESTED
|
||
|
|
pop_fpu_caller
|
||
|
|
|
||
|
|
.if (regno == 1)
|
||
|
|
setgie.d
|
||
|
|
dsb
|
||
|
|
popm $r0, $r1 /* $0 is dummy */
|
||
|
|
MTUSR_IFC "$r1"
|
||
|
|
.endif
|
||
|
|
|
||
|
|
popm $r15,$r30 /* full: 16 gpr, reduce: 4 gpr*/
|
||
|
|
popm $r0, $r5
|
||
|
|
.endm
|