401 lines
15 KiB
C
401 lines
15 KiB
C
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/*
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* File : drv_sdram.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2016, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2016-08-20 xuzhuoyi The first version for STM32F42x
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "drv_sdram.h"
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#include "stm32f4xx_fmc.h"
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#include <rtdevice.h>
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#ifndef USE_Delay
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static void delay(__IO uint32_t nCount);
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#endif /* USE_Delay*/
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/**
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* @brief Configures the FMC and GPIOs to interface with the SDRAM memory.
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* This function must be called before any read/write operation
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* on the SDRAM.
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* @param None
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* @retval None
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*/
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void SDRAM_Init(void)
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{
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FMC_SDRAMInitTypeDef FMC_SDRAMInitStructure;
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FMC_SDRAMTimingInitTypeDef FMC_SDRAMTimingInitStructure;
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/* GPIO configuration for FMC SDRAM bank */
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SDRAM_GPIOConfig();
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/* Enable FMC clock */
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RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE);
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/* FMC Configuration ---------------------------------------------------------*/
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/* FMC SDRAM Bank configuration */
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/* Timing configuration for 90 Mhz of SD clock frequency (180Mhz/2) */
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/* TMRD: 2 Clock cycles */
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FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay = 2;
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/* TXSR: min=70ns (7x11.11ns) */
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FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 7;
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/* TRAS: min=42ns (4x11.11ns) max=120k (ns) */
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FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime = 4;
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/* TRC: min=70 (7x11.11ns) */
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FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay = 7;
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/* TWR: min=1+ 7ns (1+1x11.11ns) */
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FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime = 2;
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/* TRP: 20ns => 2x11.11ns */
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FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2;
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/* TRCD: 20ns => 2x11.11ns */
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FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2;
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/* FMC SDRAM control configuration */
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FMC_SDRAMInitStructure.FMC_Bank = FMC_Bank2_SDRAM;
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/* Row addressing: [7:0] */
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FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b;
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/* Column addressing: [11:0] */
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FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_12b;
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FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = SDRAM_MEMORY_WIDTH;
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FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4;
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FMC_SDRAMInitStructure.FMC_CASLatency = SDRAM_CAS_LATENCY;
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FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable;
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FMC_SDRAMInitStructure.FMC_SDClockPeriod = SDCLOCK_PERIOD;
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FMC_SDRAMInitStructure.FMC_ReadBurst = SDRAM_READBURST;
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FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_1;
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FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure;
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/* FMC SDRAM bank initialization */
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FMC_SDRAMInit(&FMC_SDRAMInitStructure);
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/* FMC SDRAM device initialization sequence */
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SDRAM_InitSequence();
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}
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/**
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* @brief Configures all SDRAM memory I/Os pins.
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* @param None.
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* @retval None.
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*/
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void SDRAM_GPIOConfig(void)
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{
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GPIO_InitTypeDef GPIO_InitStructure;
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/* Enable GPIOs clock */
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOD |
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RCC_AHB1Periph_GPIOE | RCC_AHB1Periph_GPIOF | RCC_AHB1Periph_GPIOG, ENABLE);
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/*-- GPIOs Configuration -----------------------------------------------------*/
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/*
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+-------------------+--------------------+--------------------+--------------------+
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+ SDRAM pins assignment +
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+-------------------+--------------------+--------------------+--------------------+
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| PD0 <-> FMC_D2 | PE0 <-> FMC_NBL0 | PF0 <-> FMC_A0 | PG0 <-> FMC_A10 |
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| PD1 <-> FMC_D3 | PE1 <-> FMC_NBL1 | PF1 <-> FMC_A1 | PG1 <-> FMC_A11 |
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| PD8 <-> FMC_D13 | PE7 <-> FMC_D4 | PF2 <-> FMC_A2 | PG8 <-> FMC_SDCLK |
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| PD9 <-> FMC_D14 | PE8 <-> FMC_D5 | PF3 <-> FMC_A3 | PG15 <-> FMC_NCAS |
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| PD10 <-> FMC_D15 | PE9 <-> FMC_D6 | PF4 <-> FMC_A4 |--------------------+
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| PD14 <-> FMC_D0 | PE10 <-> FMC_D7 | PF5 <-> FMC_A5 |
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| PD15 <-> FMC_D1 | PE11 <-> FMC_D8 | PF11 <-> FMC_NRAS |
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+-------------------| PE12 <-> FMC_D9 | PF12 <-> FMC_A6 |
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| PE13 <-> FMC_D10 | PF13 <-> FMC_A7 |
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| PE14 <-> FMC_D11 | PF14 <-> FMC_A8 |
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| PE15 <-> FMC_D12 | PF15 <-> FMC_A9 |
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+-------------------+--------------------+--------------------+
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| PB5 <-> FMC_SDCKE1|
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| PB6 <-> FMC_SDNE1 |
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| PC0 <-> FMC_SDNWE |
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+-------------------+
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*/
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/* Common GPIO configuration */
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
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/* GPIOB configuration */
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GPIO_PinAFConfig(GPIOB, GPIO_PinSource5 , GPIO_AF_FMC);
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GPIO_PinAFConfig(GPIOB, GPIO_PinSource6 , GPIO_AF_FMC);
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6;
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GPIO_Init(GPIOB, &GPIO_InitStructure);
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/* GPIOC configuration */
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GPIO_PinAFConfig(GPIOC, GPIO_PinSource0 , GPIO_AF_FMC);
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
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GPIO_Init(GPIOC, &GPIO_InitStructure);
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/* GPIOD configuration */
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GPIO_PinAFConfig(GPIOD, GPIO_PinSource0, GPIO_AF_FMC);
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GPIO_PinAFConfig(GPIOD, GPIO_PinSource1, GPIO_AF_FMC);
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GPIO_PinAFConfig(GPIOD, GPIO_PinSource8, GPIO_AF_FMC);
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GPIO_PinAFConfig(GPIOD, GPIO_PinSource9, GPIO_AF_FMC);
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GPIO_PinAFConfig(GPIOD, GPIO_PinSource10, GPIO_AF_FMC);
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GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_FMC);
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GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_FMC);
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 |
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GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_14 |
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GPIO_Pin_15;
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GPIO_Init(GPIOD, &GPIO_InitStructure);
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/* GPIOE configuration */
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GPIO_PinAFConfig(GPIOE, GPIO_PinSource0 , GPIO_AF_FMC);
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GPIO_PinAFConfig(GPIOE, GPIO_PinSource1 , GPIO_AF_FMC);
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GPIO_PinAFConfig(GPIOE, GPIO_PinSource7 , GPIO_AF_FMC);
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GPIO_PinAFConfig(GPIOE, GPIO_PinSource8 , GPIO_AF_FMC);
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GPIO_PinAFConfig(GPIOE, GPIO_PinSource9 , GPIO_AF_FMC);
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GPIO_PinAFConfig(GPIOE, GPIO_PinSource10 , GPIO_AF_FMC);
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GPIO_PinAFConfig(GPIOE, GPIO_PinSource11 , GPIO_AF_FMC);
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GPIO_PinAFConfig(GPIOE, GPIO_PinSource12 , GPIO_AF_FMC);
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GPIO_PinAFConfig(GPIOE, GPIO_PinSource13 , GPIO_AF_FMC);
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GPIO_PinAFConfig(GPIOE, GPIO_PinSource14 , GPIO_AF_FMC);
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GPIO_PinAFConfig(GPIOE, GPIO_PinSource15 , GPIO_AF_FMC);
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_7 |
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GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
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GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 |
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GPIO_Pin_14 | GPIO_Pin_15;
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GPIO_Init(GPIOE, &GPIO_InitStructure);
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/* GPIOF configuration */
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GPIO_PinAFConfig(GPIOF, GPIO_PinSource0 , GPIO_AF_FMC);
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GPIO_PinAFConfig(GPIOF, GPIO_PinSource1 , GPIO_AF_FMC);
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GPIO_PinAFConfig(GPIOF, GPIO_PinSource2 , GPIO_AF_FMC);
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GPIO_PinAFConfig(GPIOF, GPIO_PinSource3 , GPIO_AF_FMC);
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GPIO_PinAFConfig(GPIOF, GPIO_PinSource4 , GPIO_AF_FMC);
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GPIO_PinAFConfig(GPIOF, GPIO_PinSource5 , GPIO_AF_FMC);
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GPIO_PinAFConfig(GPIOF, GPIO_PinSource11 , GPIO_AF_FMC);
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GPIO_PinAFConfig(GPIOF, GPIO_PinSource12 , GPIO_AF_FMC);
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GPIO_PinAFConfig(GPIOF, GPIO_PinSource13 , GPIO_AF_FMC);
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GPIO_PinAFConfig(GPIOF, GPIO_PinSource14 , GPIO_AF_FMC);
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GPIO_PinAFConfig(GPIOF, GPIO_PinSource15 , GPIO_AF_FMC);
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 |
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GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 |
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GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 |
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GPIO_Pin_14 | GPIO_Pin_15;
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GPIO_Init(GPIOF, &GPIO_InitStructure);
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/* GPIOG configuration */
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GPIO_PinAFConfig(GPIOG, GPIO_PinSource0 , GPIO_AF_FMC);
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GPIO_PinAFConfig(GPIOG, GPIO_PinSource1 , GPIO_AF_FMC);
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GPIO_PinAFConfig(GPIOG, GPIO_PinSource4 , GPIO_AF_FMC);
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GPIO_PinAFConfig(GPIOG, GPIO_PinSource5 , GPIO_AF_FMC);
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GPIO_PinAFConfig(GPIOG, GPIO_PinSource8 , GPIO_AF_FMC);
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GPIO_PinAFConfig(GPIOG, GPIO_PinSource15 , GPIO_AF_FMC);
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 |
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GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_15;
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GPIO_Init(GPIOG, &GPIO_InitStructure);
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}
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/**
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* @brief Executes the SDRAM memory initialization sequence.
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* @param None.
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* @retval None.
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*/
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void SDRAM_InitSequence(void)
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{
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FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure;
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uint32_t tmpr = 0;
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/* Step 3 --------------------------------------------------------------------*/
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/* Configure a clock configuration enable command */
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FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_CLK_Enabled;
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FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
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FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1;
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FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0;
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/* Wait until the SDRAM controller is ready */
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while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
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{
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}
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/* Send the command */
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FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
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/* Step 4 --------------------------------------------------------------------*/
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/* Insert 100 ms delay */
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__Delay(10);
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/* Step 5 --------------------------------------------------------------------*/
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/* Configure a PALL (precharge all) command */
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FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_PALL;
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FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
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FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1;
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FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0;
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/* Wait until the SDRAM controller is ready */
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while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
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{
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}
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/* Send the command */
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FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
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/* Step 6 --------------------------------------------------------------------*/
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/* Configure a Auto-Refresh command */
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FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_AutoRefresh;
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FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
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FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 4;
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FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0;
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/* Wait until the SDRAM controller is ready */
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while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
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{
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}
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/* Send the first command */
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FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
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/* Wait until the SDRAM controller is ready */
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while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
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{
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}
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/* Send the second command */
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FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
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/* Step 7 --------------------------------------------------------------------*/
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/* Program the external memory mode register */
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tmpr = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_2 |
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SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |
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SDRAM_MODEREG_CAS_LATENCY_3 |
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SDRAM_MODEREG_OPERATING_MODE_STANDARD |
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SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
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/* Configure a load Mode register command*/
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FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_LoadMode;
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FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
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FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1;
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FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = tmpr;
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/* Wait until the SDRAM controller is ready */
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while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
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{
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}
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/* Send the command */
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FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
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/* Step 8 --------------------------------------------------------------------*/
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/* Set the refresh rate counter */
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/* (15.62 us x Freq) - 20 */
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/* Set the device refresh counter */
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FMC_SetRefreshCount(1386);
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/* Wait until the SDRAM controller is ready */
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while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
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{
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}
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|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Writes a Entire-word buffer to the SDRAM memory.
|
||
|
|
* @param pBuffer: pointer to buffer.
|
||
|
|
* @param uwWriteAddress: SDRAM memory internal address from which the data will be
|
||
|
|
* written.
|
||
|
|
* @param uwBufferSize: number of words to write.
|
||
|
|
* @retval None.
|
||
|
|
*/
|
||
|
|
void SDRAM_WriteBuffer(uint32_t* pBuffer, uint32_t uwWriteAddress, uint32_t uwBufferSize)
|
||
|
|
{
|
||
|
|
__IO uint32_t write_pointer = (uint32_t)uwWriteAddress;
|
||
|
|
|
||
|
|
/* Disable write protection */
|
||
|
|
FMC_SDRAMWriteProtectionConfig(FMC_Bank2_SDRAM, DISABLE);
|
||
|
|
|
||
|
|
/* Wait until the SDRAM controller is ready */
|
||
|
|
while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
|
||
|
|
{
|
||
|
|
}
|
||
|
|
|
||
|
|
/* While there is data to write */
|
||
|
|
for (; uwBufferSize != 0; uwBufferSize--)
|
||
|
|
{
|
||
|
|
/* Transfer data to the memory */
|
||
|
|
*(uint32_t *) (SDRAM_BANK_ADDR + write_pointer) = *pBuffer++;
|
||
|
|
|
||
|
|
/* Increment the address*/
|
||
|
|
write_pointer += 4;
|
||
|
|
}
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Reads data buffer from the SDRAM memory.
|
||
|
|
* @param pBuffer: pointer to buffer.
|
||
|
|
* @param ReadAddress: SDRAM memory internal address from which the data will be
|
||
|
|
* read.
|
||
|
|
* @param uwBufferSize: number of words to write.
|
||
|
|
* @retval None.
|
||
|
|
*/
|
||
|
|
void SDRAM_ReadBuffer(uint32_t* pBuffer, uint32_t uwReadAddress, uint32_t uwBufferSize)
|
||
|
|
{
|
||
|
|
__IO uint32_t write_pointer = (uint32_t)uwReadAddress;
|
||
|
|
|
||
|
|
|
||
|
|
/* Wait until the SDRAM controller is ready */
|
||
|
|
while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
|
||
|
|
{
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Read data */
|
||
|
|
for(; uwBufferSize != 0x00; uwBufferSize--)
|
||
|
|
{
|
||
|
|
*pBuffer++ = *(__IO uint32_t *)(SDRAM_BANK_ADDR + write_pointer );
|
||
|
|
|
||
|
|
/* Increment the address*/
|
||
|
|
write_pointer += 4;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
#ifndef USE_Delay
|
||
|
|
/**
|
||
|
|
* @brief Inserts a delay time.
|
||
|
|
* @param nCount: specifies the delay time length.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
static void delay(__IO uint32_t nCount)
|
||
|
|
{
|
||
|
|
__IO uint32_t index = 0;
|
||
|
|
for(index = (100000 * nCount); index != 0; index--)
|
||
|
|
{
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#endif /* USE_Delay */
|
||
|
|
|
||
|
|
rt_err_t sdram_hw_init(void)
|
||
|
|
{
|
||
|
|
SDRAM_Init();
|
||
|
|
return RT_EOK;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int rt_sdram_hw_init(void)
|
||
|
|
{
|
||
|
|
return (int)sdram_hw_init();
|
||
|
|
}
|
||
|
|
INIT_BOARD_EXPORT(rt_sdram_hw_init);
|