2013-01-08 21:05:02 +08:00
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#ifndef __JZ4740_H__
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#define __JZ4740_H__
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#include "jz47xx.h"
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#define WDT_BASE 0xB0002000
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/* Watchdog */
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#define WDT_TDR __REG16(WDT_BASE + 0x00) /* Watchdog Timer Data Register */
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#define WDT_TCER __REG8(WDT_BASE + 0x04) /* Watchdog Counter Enable Register */
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#define WDT_TCNT __REG16(WDT_BASE + 0x08) /* Watchdog Timer Counter Register */
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#define WDT_TCSR __REG16(WDT_BASE + 0x0C) /* Watchdog Timer Control Register */
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/* Clock Gate Register Definitions */
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#define CPM_CLKGR_UART1 (1 << 15)
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#define CPM_CLKGR_UHC (1 << 14)
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#define CPM_CLKGR_IPU (1 << 13)
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#define CPM_CLKGR_DMAC (1 << 12)
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#define CPM_CLKGR_UDC (1 << 11)
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#define CPM_CLKGR_LCD (1 << 10)
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#define CPM_CLKGR_CIM (1 << 9)
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#define CPM_CLKGR_SADC (1 << 8)
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#define CPM_CLKGR_MSC (1 << 7)
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#define CPM_CLKGR_AIC1 (1 << 6)
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#define CPM_CLKGR_AIC2 (1 << 5)
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#define CPM_CLKGR_SSI (1 << 4)
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#define CPM_CLKGR_I2C (1 << 3)
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#define CPM_CLKGR_RTC (1 << 2)
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#define CPM_CLKGR_TCU (1 << 1)
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#define CPM_CLKGR_UART0 (1 << 0)
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/* Interrupt Definitions */
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#define IRQ_I2C 1
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#define IRQ_UHC 3
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#define IRQ_UART0 9
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#define IRQ_SADC 12
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#define IRQ_MSC 14
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#define IRQ_RTC 15
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#define IRQ_SSI 16
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#define IRQ_CIM 17
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#define IRQ_AIC 18
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#define IRQ_ETH 19
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#define IRQ_DMAC 20
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#define IRQ_TCU2 21
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#define IRQ_TCU1 22
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#define IRQ_TCU0 23
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#define IRQ_UDC 24
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#define IRQ_GPIO3 25
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#define IRQ_GPIO2 26
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#define IRQ_GPIO1 27
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#define IRQ_GPIO0 28
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#define IRQ_IPU 29
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#define IRQ_LCD 30
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#endif
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