406 lines
14 KiB
C
406 lines
14 KiB
C
|
/*
|
||
|
|
* File : board.c
|
||
|
|
* This file is part of RT-Thread RTOS
|
||
|
|
* COPYRIGHT (C) 2006 - 2009 RT-Thread Develop Team
|
||
|
|
*
|
||
|
|
* The license and distribution terms for this file may be
|
||
|
|
* found in the file LICENSE in this distribution or at
|
||
|
|
* http://openlab.rt-thread.com/license/LICENSE
|
||
|
|
*
|
||
|
|
* Change Logs:
|
||
|
|
* Date Author Notes
|
||
|
|
* 2006-08-23 Bernard first implementation
|
||
|
|
*/
|
||
|
|
|
||
|
|
#include <rthw.h>
|
||
|
|
#include <rtthread.h>
|
||
|
|
|
||
|
|
#include "stm32f10x_lib.h"
|
||
|
|
|
||
|
|
static void rt_hw_console_init(void);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @addtogroup STM32
|
||
|
|
*/
|
||
|
|
|
||
|
|
/*@{*/
|
||
|
|
|
||
|
|
ErrorStatus HSEStartUpStatus;
|
||
|
|
|
||
|
|
/*******************************************************************************
|
||
|
|
* Function Name : RCC_Configuration
|
||
|
|
* Description : Configures the different system clocks.
|
||
|
|
* Input : None
|
||
|
|
* Output : None
|
||
|
|
* Return : None
|
||
|
|
*******************************************************************************/
|
||
|
|
void RCC_Configuration(void)
|
||
|
|
{
|
||
|
|
/* RCC system reset(for debug purpose) */
|
||
|
|
RCC_DeInit();
|
||
|
|
|
||
|
|
/* Enable HSE */
|
||
|
|
RCC_HSEConfig(RCC_HSE_ON);
|
||
|
|
|
||
|
|
/* Wait till HSE is ready */
|
||
|
|
HSEStartUpStatus = RCC_WaitForHSEStartUp();
|
||
|
|
|
||
|
|
if(HSEStartUpStatus == SUCCESS)
|
||
|
|
{
|
||
|
|
/* HCLK = SYSCLK */
|
||
|
|
RCC_HCLKConfig(RCC_SYSCLK_Div1);
|
||
|
|
|
||
|
|
/* PCLK2 = HCLK */
|
||
|
|
RCC_PCLK2Config(RCC_HCLK_Div1);
|
||
|
|
/* PCLK1 = HCLK/2 */
|
||
|
|
RCC_PCLK1Config(RCC_HCLK_Div2);
|
||
|
|
|
||
|
|
/* Flash 2 wait state */
|
||
|
|
FLASH_SetLatency(FLASH_Latency_2);
|
||
|
|
/* Enable Prefetch Buffer */
|
||
|
|
FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
|
||
|
|
|
||
|
|
/* PLLCLK = 8MHz * 9 = 72 MHz */
|
||
|
|
RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);
|
||
|
|
|
||
|
|
/* Enable PLL */
|
||
|
|
RCC_PLLCmd(ENABLE);
|
||
|
|
|
||
|
|
/* Wait till PLL is ready */
|
||
|
|
while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) ;
|
||
|
|
|
||
|
|
/* Select PLL as system clock source */
|
||
|
|
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
|
||
|
|
|
||
|
|
/* Wait till PLL is used as system clock source */
|
||
|
|
while(RCC_GetSYSCLKSource() != 0x08) ;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*******************************************************************************
|
||
|
|
* Function Name : NVIC_Configuration
|
||
|
|
* Description : Configures Vector Table base location.
|
||
|
|
* Input : None
|
||
|
|
* Output : None
|
||
|
|
* Return : None
|
||
|
|
*******************************************************************************/
|
||
|
|
void NVIC_Configuration(void)
|
||
|
|
{
|
||
|
|
#ifdef VECT_TAB_RAM
|
||
|
|
/* Set the Vector Table base location at 0x20000000 */
|
||
|
|
NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
|
||
|
|
#else /* VECT_TAB_FLASH */
|
||
|
|
/* Set the Vector Table base location at 0x08000000 */
|
||
|
|
NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
/*******************************************************************************
|
||
|
|
* Function Name : SysTick_Configuration
|
||
|
|
* Description : Configures the SysTick for OS tick.
|
||
|
|
* Input : None
|
||
|
|
* Output : None
|
||
|
|
* Return : None
|
||
|
|
*******************************************************************************/
|
||
|
|
void SysTick_Configuration(void)
|
||
|
|
{
|
||
|
|
RCC_ClocksTypeDef rcc_clocks;
|
||
|
|
rt_uint32_t cnts;
|
||
|
|
|
||
|
|
RCC_GetClocksFreq(&rcc_clocks);
|
||
|
|
|
||
|
|
cnts = (rt_uint32_t)rcc_clocks.HCLK_Frequency / RT_TICK_PER_SECOND;
|
||
|
|
|
||
|
|
SysTick_SetReload(cnts);
|
||
|
|
SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK);
|
||
|
|
SysTick_CounterCmd(SysTick_Counter_Enable);
|
||
|
|
SysTick_ITConfig(ENABLE);
|
||
|
|
}
|
||
|
|
|
||
|
|
extern void rt_hw_interrupt_thread_switch(void);
|
||
|
|
/**
|
||
|
|
* This is the timer interrupt service routine.
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
void rt_hw_timer_handler(void)
|
||
|
|
{
|
||
|
|
/* enter interrupt */
|
||
|
|
rt_interrupt_enter();
|
||
|
|
|
||
|
|
rt_tick_increase();
|
||
|
|
|
||
|
|
/* leave interrupt */
|
||
|
|
rt_interrupt_leave();
|
||
|
|
rt_hw_interrupt_thread_switch();
|
||
|
|
}
|
||
|
|
|
||
|
|
/*******************************************************************************
|
||
|
|
* Function Name : FSMC_SRAM_Init
|
||
|
|
* Description : Configures the FSMC and GPIOs to interface with the SRAM memory.
|
||
|
|
* This function must be called before any write/read operation
|
||
|
|
* on the SRAM.
|
||
|
|
* Input : None
|
||
|
|
* Output : None
|
||
|
|
* Return : None
|
||
|
|
*******************************************************************************/
|
||
|
|
void FSMC_SRAM_Init(void)
|
||
|
|
{
|
||
|
|
FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure;
|
||
|
|
FSMC_NORSRAMTimingInitTypeDef p;
|
||
|
|
GPIO_InitTypeDef GPIO_InitStructure;
|
||
|
|
|
||
|
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOG | RCC_APB2Periph_GPIOE |
|
||
|
|
RCC_APB2Periph_GPIOF, ENABLE);
|
||
|
|
|
||
|
|
/*-- GPIO Configuration ------------------------------------------------------*/
|
||
|
|
/* SRAM Data lines configuration */
|
||
|
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 |
|
||
|
|
GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15;
|
||
|
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
|
||
|
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||
|
|
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||
|
|
|
||
|
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
|
||
|
|
GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 |
|
||
|
|
GPIO_Pin_15;
|
||
|
|
GPIO_Init(GPIOE, &GPIO_InitStructure);
|
||
|
|
|
||
|
|
/* SRAM Address lines configuration */
|
||
|
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
|
||
|
|
GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 |
|
||
|
|
GPIO_Pin_14 | GPIO_Pin_15;
|
||
|
|
GPIO_Init(GPIOF, &GPIO_InitStructure);
|
||
|
|
|
||
|
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
|
||
|
|
GPIO_Pin_4 | GPIO_Pin_5;
|
||
|
|
GPIO_Init(GPIOG, &GPIO_InitStructure);
|
||
|
|
|
||
|
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13;
|
||
|
|
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||
|
|
|
||
|
|
/* NOE and NWE configuration */
|
||
|
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 |GPIO_Pin_5;
|
||
|
|
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||
|
|
|
||
|
|
/* NE3 configuration */
|
||
|
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
|
||
|
|
GPIO_Init(GPIOG, &GPIO_InitStructure);
|
||
|
|
|
||
|
|
/* NBL0, NBL1 configuration */
|
||
|
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1;
|
||
|
|
GPIO_Init(GPIOE, &GPIO_InitStructure);
|
||
|
|
|
||
|
|
/*-- FSMC Configuration ------------------------------------------------------*/
|
||
|
|
p.FSMC_AddressSetupTime = 0;
|
||
|
|
p.FSMC_AddressHoldTime = 0;
|
||
|
|
p.FSMC_DataSetupTime = 2;
|
||
|
|
p.FSMC_BusTurnAroundDuration = 0;
|
||
|
|
p.FSMC_CLKDivision = 0;
|
||
|
|
p.FSMC_DataLatency = 0;
|
||
|
|
p.FSMC_AccessMode = FSMC_AccessMode_A;
|
||
|
|
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
|
||
|
|
|
||
|
|
FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
|
||
|
|
|
||
|
|
/* Enable FSMC Bank1_SRAM Bank */
|
||
|
|
FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*******************************************************************************
|
||
|
|
* Function Name : FSMC_NOR_Init
|
||
|
|
* Description : Configures the FSMC and GPIOs to interface with the NOR memory.
|
||
|
|
* This function must be called before any write/read operation
|
||
|
|
* on the NOR.
|
||
|
|
* Input : None
|
||
|
|
* Output : None
|
||
|
|
* Return : None
|
||
|
|
*******************************************************************************/
|
||
|
|
void FSMC_NOR_Init(void)
|
||
|
|
{
|
||
|
|
FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure;
|
||
|
|
FSMC_NORSRAMTimingInitTypeDef p;
|
||
|
|
GPIO_InitTypeDef GPIO_InitStructure;
|
||
|
|
|
||
|
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE |
|
||
|
|
RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG, ENABLE);
|
||
|
|
|
||
|
|
/*-- GPIO Configuration ------------------------------------------------------*/
|
||
|
|
/* NOR Data lines configuration */
|
||
|
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 |
|
||
|
|
GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15;
|
||
|
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
|
||
|
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||
|
|
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||
|
|
|
||
|
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
|
||
|
|
GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 |
|
||
|
|
GPIO_Pin_14 | GPIO_Pin_15;
|
||
|
|
GPIO_Init(GPIOE, &GPIO_InitStructure);
|
||
|
|
|
||
|
|
/* NOR Address lines configuration */
|
||
|
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
|
||
|
|
GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 |
|
||
|
|
GPIO_Pin_14 | GPIO_Pin_15;
|
||
|
|
GPIO_Init(GPIOF, &GPIO_InitStructure);
|
||
|
|
|
||
|
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 |
|
||
|
|
GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5;
|
||
|
|
GPIO_Init(GPIOG, &GPIO_InitStructure);
|
||
|
|
|
||
|
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13;
|
||
|
|
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||
|
|
|
||
|
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6;
|
||
|
|
GPIO_Init(GPIOE, &GPIO_InitStructure);
|
||
|
|
|
||
|
|
/* NOE and NWE configuration */
|
||
|
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5;
|
||
|
|
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||
|
|
|
||
|
|
/* NE2 configuration */
|
||
|
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
|
||
|
|
GPIO_Init(GPIOG, &GPIO_InitStructure);
|
||
|
|
|
||
|
|
/*-- FSMC Configuration ----------------------------------------------------*/
|
||
|
|
p.FSMC_AddressSetupTime = 0x03;
|
||
|
|
p.FSMC_AddressHoldTime = 0x00;
|
||
|
|
p.FSMC_DataSetupTime = 0x04;
|
||
|
|
p.FSMC_BusTurnAroundDuration = 0x00;
|
||
|
|
p.FSMC_CLKDivision = 0x00;
|
||
|
|
p.FSMC_DataLatency = 0x00;
|
||
|
|
p.FSMC_AccessMode = FSMC_AccessMode_B;
|
||
|
|
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_NOR;
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
|
||
|
|
|
||
|
|
FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
|
||
|
|
|
||
|
|
/* Enable FSMC Bank1_NOR Bank */
|
||
|
|
FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* This function will initial STM32 board.
|
||
|
|
*/
|
||
|
|
void rt_hw_board_init()
|
||
|
|
{
|
||
|
|
/* Configure the system clocks */
|
||
|
|
RCC_Configuration();
|
||
|
|
|
||
|
|
/* NVIC Configuration */
|
||
|
|
NVIC_Configuration();
|
||
|
|
|
||
|
|
/* SRAM init */
|
||
|
|
FSMC_SRAM_Init();
|
||
|
|
|
||
|
|
/* Configure the SysTick */
|
||
|
|
SysTick_Configuration();
|
||
|
|
|
||
|
|
rt_hw_console_init();
|
||
|
|
}
|
||
|
|
|
||
|
|
/* init console to support rt_kprintf */
|
||
|
|
static void rt_hw_console_init()
|
||
|
|
{
|
||
|
|
/* Enable USART1 and GPIOA clocks */
|
||
|
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE);
|
||
|
|
|
||
|
|
/* GPIO configuration */
|
||
|
|
{
|
||
|
|
GPIO_InitTypeDef GPIO_InitStructure;
|
||
|
|
|
||
|
|
/* Configure USART1 Tx (PA.09) as alternate function push-pull */
|
||
|
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
|
||
|
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
|
||
|
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||
|
|
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||
|
|
|
||
|
|
/* Configure USART1 Rx (PA.10) as input floating */
|
||
|
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
|
||
|
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
|
||
|
|
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* USART configuration */
|
||
|
|
{
|
||
|
|
USART_InitTypeDef USART_InitStructure;
|
||
|
|
|
||
|
|
/* USART1 configured as follow:
|
||
|
|
- BaudRate = 115200 baud
|
||
|
|
- Word Length = 8 Bits
|
||
|
|
- One Stop Bit
|
||
|
|
- No parity
|
||
|
|
- Hardware flow control disabled (RTS and CTS signals)
|
||
|
|
- Receive and transmit enabled
|
||
|
|
- USART Clock disabled
|
||
|
|
- USART CPOL: Clock is active low
|
||
|
|
- USART CPHA: Data is captured on the middle
|
||
|
|
- USART LastBit: The clock pulse of the last data bit is not output to
|
||
|
|
the SCLK pin
|
||
|
|
*/
|
||
|
|
USART_InitStructure.USART_BaudRate = 115200;
|
||
|
|
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
|
||
|
|
USART_InitStructure.USART_StopBits = USART_StopBits_1;
|
||
|
|
USART_InitStructure.USART_Parity = USART_Parity_No;
|
||
|
|
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
|
||
|
|
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
|
||
|
|
USART_Init(USART1, &USART_InitStructure);
|
||
|
|
/* Enable USART1 */
|
||
|
|
USART_Cmd(USART1, ENABLE);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* write one character to serial, must not trigger interrupt */
|
||
|
|
static void rt_hw_console_putc(const char c)
|
||
|
|
{
|
||
|
|
/*
|
||
|
|
to be polite with serial console add a line feed
|
||
|
|
to the carriage return character
|
||
|
|
*/
|
||
|
|
if (c=='\n')rt_hw_console_putc('\r');
|
||
|
|
|
||
|
|
while (!(USART1->SR & USART_FLAG_TXE));
|
||
|
|
USART1->DR = (c & 0x1FF);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* This function is used by rt_kprintf to display a string on console.
|
||
|
|
*
|
||
|
|
* @param str the displayed string
|
||
|
|
*/
|
||
|
|
void rt_hw_console_output(const char* str)
|
||
|
|
{
|
||
|
|
while (*str)
|
||
|
|
{
|
||
|
|
rt_hw_console_putc (*str++);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*@}*/
|