240 lines
6.8 KiB
C
240 lines
6.8 KiB
C
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/*
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* Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*!
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* @file gpt.c
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* @brief GPT driver source file.
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*
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* @ingroup diag_timer
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*/
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#include "sdk.h"
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#include "gpt.h"
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#include "imx_timer.h"
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#include "registers/regsgpt.h"
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#include "interrupt.h"
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#include "ccm_pll.h"
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////////////////////////////////////////////////////////////////////////////////
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// Code
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////////////////////////////////////////////////////////////////////////////////
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static inline void gpt_clear_all_events(void)
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{
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HW_GPT_SR_WR(kGPTAllEvents);
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}
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uint32_t gpt_get_rollover_event(void)
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{
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// clear it if found set
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if (HW_GPT_SR.B.ROV)
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{
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HW_GPT_SR_WR(BM_GPT_SR_ROV);
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return kGPTRollover;
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}
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// return the read value before the bit was cleared
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return 0;
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}
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uint32_t gpt_get_capture_event(uint8_t flag, uint32_t * capture_val)
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{
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// get the capture status bit
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flag &= kGPTInputCapture1 | kGPTInputCapture2;
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uint32_t status_register = HW_GPT_SR_RD() & flag;
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// Read the captured timer value.
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if (capture_val)
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{
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if (status_register == kGPTInputCapture1)
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{
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*(uint32_t *) capture_val = HW_GPT_ICR1.B.CAPT;
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}
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else if (status_register == kGPTInputCapture2)
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{
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*(uint32_t *) capture_val = HW_GPT_ICR2.B.CAPT;
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}
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}
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// Clear the flag.
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HW_GPT_SR_WR(status_register);
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// return the read value before the bit was cleared
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return status_register;
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}
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void gpt_set_capture_event(uint8_t cap_input, uint8_t cap_input_mode)
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{
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// set the new input mode
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switch (cap_input)
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{
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case kGPTInputCapture1:
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HW_GPT_CR.B.IM1 = cap_input_mode;
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break;
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case kGPTInputCapture2:
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HW_GPT_CR.B.IM2 = cap_input_mode;
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break;
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}
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}
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uint32_t gpt_get_compare_event(uint8_t flag)
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{
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// get the active compare flags
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flag &= kGPTOutputCompare1 | kGPTOutputCompare2 | kGPTOutputCompare3;
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uint32_t status_register = HW_GPT_SR_RD() & flag;
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// clear flags which are active
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if (status_register)
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{
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HW_GPT_SR_WR(status_register);
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}
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// return the read value before the flags were cleared
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return status_register;
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}
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void gpt_set_compare_event(uint8_t cmp_output, uint8_t cmp_output_mode, uint32_t cmp_value)
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{
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// set the value to compare with
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switch (cmp_output)
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{
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case kGPTOutputCompare1:
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BW_GPT_CR_OM1(cmp_output_mode);
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HW_GPT_OCR1_WR(cmp_value);
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break;
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case kGPTOutputCompare2:
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BW_GPT_CR_OM2(cmp_output_mode);
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HW_GPT_OCR2_WR(cmp_value);
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break;
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case kGPTOutputCompare3:
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BW_GPT_CR_OM3(cmp_output_mode);
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HW_GPT_OCR3_WR(cmp_value);
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break;
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}
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}
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void gpt_counter_disable(void)
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{
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// disable the counter
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HW_GPT_CR.B.EN = 0;
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// ensure to leave the counter in a proper state by disabling the interrupt sources
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HW_GPT_IR_WR(0);
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// and by clearing possible remaining events
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gpt_clear_all_events();
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}
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void gpt_counter_enable(uint32_t irq_mode)
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{
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// ensure to start the counter in a proper state by clearing possible remaining events
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gpt_clear_all_events();
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// enable the interrupts or clear the register for polling
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HW_GPT_IR_WR(irq_mode & kGPTAllEvents);
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// finally, enable the counter
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HW_GPT_CR.B.EN = 1;
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}
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void gpt_setup_interrupt(void (*irq_subroutine)(void), bool enableIt)
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{
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uint32_t irq_id = IMX_INT_GPT;
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if (enableIt)
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{
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// register the IRQ sub-routine
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register_interrupt_routine(irq_id, irq_subroutine);
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// enable the IRQ
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enable_interrupt(irq_id, CPU_0, 0);
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}
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else
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{
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// disable the IRQ
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disable_interrupt(irq_id, CPU_0);
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}
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}
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void gpt_init(uint32_t clock_src, uint32_t prescaler, uint32_t counter_mode, uint32_t low_power_mode)
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{
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uint32_t control_reg_tmp = 0;
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uint32_t base = GPT_BASE_ADDR;
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// enable the source clocks to the GPT port
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clock_gating_config(base, CLOCK_ON);
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// start with a known state by disabling and reseting the module
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HW_GPT_CR_WR(BM_GPT_CR_SWR);
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// wait for the reset to complete
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while (HW_GPT_CR.B.SWR != 0) ;
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// set the reference source clock for the counter
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if (clock_src == CLKSRC_CKIL)
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{
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// CKIL source is 0x4 for GPT but 0x3 for EPIT
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clock_src++;
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}
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control_reg_tmp |= BF_GPT_CR_CLKSRC(clock_src);
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// the prescaler can be changed at any time, and
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// this affects the output clock immediately
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HW_GPT_PR_WR(BF_GPT_PR_PRESCALER(prescaler - 1));
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// set the counter mode
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control_reg_tmp |= BF_GPT_CR_FRR(counter_mode);
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// set behavior for low power mode
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if (low_power_mode & WAIT_MODE_EN)
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{
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control_reg_tmp |= BM_GPT_CR_WAITEN;
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}
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if (low_power_mode & STOP_MODE_EN)
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{
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control_reg_tmp |= BM_GPT_CR_STOPEN;
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}
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// specify from where the counter starts to count when enabled
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// this code makes it start from 0
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control_reg_tmp |= BM_GPT_CR_ENMOD;
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// finally write the control register
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HW_GPT_CR_WR(control_reg_tmp);
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}
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////////////////////////////////////////////////////////////////////////////////
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// EOF
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////////////////////////////////////////////////////////////////////////////////
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